On Thu, Nov 30, 2017 at 08:56:42PM +0000, Chris Wilson wrote: > Quoting Lucas Stach (2017-11-30 17:34:28) > > Dma-bufs should already be device coherent, as they are only pulled in the > > CPU domain via the begin/end cpu_access calls. As we cache the mapping set > > up by dma_map_sg a CPU sync at this point will not actually guarantee proper > > coherency on non-coherent architectures, so we can as well stop pretending. > > That matches my understanding of the dma-buf API, device coherent with > explicit cpu coherency managed by ioctl. > > > This is an important performance fix for architectures which need explicit > > cache synchronization and userspace doing lots of dma-buf imports. > > Improves Weston on Etnaviv performance 5x, where before this patch > 90% > > of Weston CPU time was spent synchronizing caches for buffers which are > > already device coherent. > > > > Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > > Sent an equivalent patch through i915's CI, which didn't show any > problems. > > Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Pushed to drm-misc-next, thx for patch&review. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
