> -----Original Message----- > From: Emil Velikov [mailto:emil.l.velikov@xxxxxxxxx] > Sent: Tuesday, November 28, 2017 9:38 AM > To: Hyun Kwon <hyunk@xxxxxxxxxx> > Cc: Daniel Vetter <daniel@xxxxxxxx>; monstr@xxxxxxxxx; David Airlie > <airlied@xxxxxxxx>; ML dri-devel <dri-devel@xxxxxxxxxxxxxxxxxxxxx>; Daniel > Vetter <daniel.vetter@xxxxxxxxx>; Jeff Mouroux <jmouroux@xxxxxxxxxx>; Satish > Kumar Nagireddy <SATISHNA@xxxxxxxxxx>; Laurent Pinchart > <laurent.pinchart@xxxxxxxxxxxxxxxx> > Subject: Re: [PATCH 0/3] Adding new drm formats needed by Xilinx IPs > > On 28 November 2017 at 17:26, Hyun Kwon <hyunk@xxxxxxxxxx> wrote: > > > > > >> -----Original Message----- > >> From: Emil Velikov [mailto:emil.l.velikov@xxxxxxxxx] > >> Sent: Tuesday, November 28, 2017 7:02 AM > >> To: Daniel Vetter <daniel@xxxxxxxx> > >> Cc: Hyun Kwon <hyunk@xxxxxxxxxx>; monstr@xxxxxxxxx; David Airlie > >> <airlied@xxxxxxxx>; ML dri-devel <dri-devel@xxxxxxxxxxxxxxxxxxxxx>; Daniel > >> Vetter <daniel.vetter@xxxxxxxxx>; Jeff Mouroux <jmouroux@xxxxxxxxxx>; > >> Satish Kumar Nagireddy <SATISHNA@xxxxxxxxxx>; Laurent Pinchart > >> <laurent.pinchart@xxxxxxxxxxxxxxxx> > >> Subject: Re: [PATCH 0/3] Adding new drm formats needed by Xilinx IPs > >> > >> On 28 November 2017 at 11:09, Daniel Vetter <daniel@xxxxxxxx> wrote: > >> > On Mon, Nov 27, 2017 at 06:27:30PM -0800, Hyun Kwon wrote: > >> >> Hi, > >> >> > >> >> This series is to add new drm formats needed by some Xilinx IPs. > >> >> Some formats have unique characteristics such as pixels not being > >> >> byte-aligned. For instance, some 10bit formats have 2bit padding > >> >> after every 3-10bit components: > >> >> > >> >> 32b[0]: 10b comp0 - 10b comp1 - 10b comp2 - 2b padding > >> >> 32b[1]: 10b comp3 - 10b comp4 - 10b comp5 - 2b padding > >> >> ... > >> >> > >> >> To model this, additional information is added to struct > >> drm_format_info. > >> >> The patch has been tested with downstream drivers as well as the > >> downstream > >> >> user space component (ex, modified modetest). > >> >> > >> >> Thanks, > >> >> hyun > >> >> > >> >> Jeffrey Mouroux (2): > >> >> uapi: drm: New fourcc codes needed by Xilinx Video IP > >> >> drm: fourcc: Update DRM Framework with new fourcc codes > >> >> > >> >> Satish Kumar Nagireddy (1): > >> >> drm: drm_fourcc: Add scaling and padding factor to drm_format_info > >> > > >> > We need the driver for this. > >> > >> To elaborate this in different light: > >> Without an upstream user (both kernel and userspace) this will be in a > >> perpetual broken state. > >> If the Xilinx DRM driver is still far off, one could update any of the > >> existing drivers - say i915 :-P > > > > Fair enough. This patch will have to wait until any client code can be > upstreamed along with. > > > Humble suggestion: try to upstream the basic functionality of your > driver as early as possible. > DRM evolves rapidly, so any lingering work will require serious work > to rebase and ensure it works. > > Quick skim at the Xilinx repository shows that initial work was done > as back as 2013 [2] :-\ Thanks for the suggestion, and I agree. Xilinx has more downstream stuff than what you can see from that repo. Thanks, -hyun > > -Emil > [1] https://github.com/Xilinx/linux-xlnx > [2] https://github.com/Xilinx/linux- > xlnx/commit/aa76be1358005c42fadb2c7e9ac58a71a141dd7b _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
