Re: [PATCH libdrm 1/2] headers: Sync amdgpu_drm.h with drm-next

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Both patches:

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@xxxxxxx>


On 20.10.2017 16:57, Andres Rodriguez wrote:
Generated using make headers_install from:
airlied/drm-next 282dc83 Merge tag 'drm-intel-next-2017-10-12' ...

Signed-off-by: Andres Rodriguez <andresx7@xxxxxxxxx>
---
  include/drm/amdgpu_drm.h | 31 ++++++++++++++++++++++++++++++-
  1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 4c6e8c4..ff01818 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -53,6 +53,7 @@ extern "C" {
  #define DRM_AMDGPU_WAIT_FENCES		0x12
  #define DRM_AMDGPU_VM			0x13
  #define DRM_AMDGPU_FENCE_TO_HANDLE	0x14
+#define DRM_AMDGPU_SCHED		0x15
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
  #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -69,6 +70,7 @@ extern "C" {
  #define DRM_IOCTL_AMDGPU_WAIT_FENCES	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
  #define DRM_IOCTL_AMDGPU_VM		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
  #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
+#define DRM_IOCTL_AMDGPU_SCHED		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
  #define AMDGPU_GEM_DOMAIN_GTT		0x2
@@ -91,6 +93,8 @@ extern "C" {
  #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS	(1 << 5)
  /* Flag that BO is always valid in this VM */
  #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID	(1 << 6)
+/* Flag that BO sharing will be explicitly synchronized */
+#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC		(1 << 7)
struct drm_amdgpu_gem_create_in {
  	/** the requested memory size */
@@ -166,13 +170,22 @@ union drm_amdgpu_bo_list {
  /* unknown cause */
  #define AMDGPU_CTX_UNKNOWN_RESET	3
+/* Context priority level */
+#define AMDGPU_CTX_PRIORITY_UNSET       -2048
+#define AMDGPU_CTX_PRIORITY_VERY_LOW    -1023
+#define AMDGPU_CTX_PRIORITY_LOW         -512
+#define AMDGPU_CTX_PRIORITY_NORMAL      0
+/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
+#define AMDGPU_CTX_PRIORITY_HIGH        512
+#define AMDGPU_CTX_PRIORITY_VERY_HIGH   1023
+
  struct drm_amdgpu_ctx_in {
  	/** AMDGPU_CTX_OP_* */
  	__u32	op;
  	/** For future use, no flags defined so far */
  	__u32	flags;
  	__u32	ctx_id;
-	__u32	_pad;
+	__s32	priority;
  };
union drm_amdgpu_ctx_out {
@@ -216,6 +229,21 @@ union drm_amdgpu_vm {
  	struct drm_amdgpu_vm_out out;
  };
+/* sched ioctl */
+#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE	1
+
+struct drm_amdgpu_sched_in {
+	/* AMDGPU_SCHED_OP_* */
+	__u32	op;
+	__u32	fd;
+	__s32	priority;
+	__u32	flags;
+};
+
+union drm_amdgpu_sched {
+	struct drm_amdgpu_sched_in in;
+};
+
  /*
   * This is not a reliable API and you should expect it to fail for any
   * number of reasons and have fallback path that do not use userptr to
@@ -629,6 +657,7 @@ struct drm_amdgpu_cs_chunk_data {
  	#define AMDGPU_INFO_SENSOR_VDDGFX		0x7
  /* Number of VRAM page faults on CPU access. */
  #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS	0x1E
+#define AMDGPU_INFO_VRAM_LOST_COUNTER		0x1F
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
  #define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff



--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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