In uvd encode parameter package, parameters input_pic_luma_pitch and input_pic_chroma_pitch should be picture width align with hardware alignment. The hardware alignment is 16 for amdgpu family earlier than AMDGPU_FAMILY_AI, and 256 for later than and including AMDGPU_FAMILY_AI. Signed-off-by: James Zhu <James.Zhu@xxxxxxx> --- tests/amdgpu/uvd_enc_tests.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c index 7518103..bbda131 100644 --- a/tests/amdgpu/uvd_enc_tests.c +++ b/tests/amdgpu/uvd_enc_tests.c @@ -272,7 +272,7 @@ static void amdgpu_cs_uvd_enc_create(void) static void check_result(struct amdgpu_uvd_enc *enc) { uint64_t sum; - uint32_t s = 26382; + uint32_t s = 175602; uint32_t *ptr, size; int i, j, r; @@ -463,6 +463,8 @@ static void amdgpu_cs_uvd_enc_encode(void) ib_cpu[len++] = chroma_offset >> 32; ib_cpu[len++] = chroma_offset; memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param)); + ib_cpu[len] = ALIGN(enc.width, align); + ib_cpu[len + 1] = ALIGN(enc.width, align); len += sizeof(uve_encode_param) / 4; memcpy((ib_cpu + len), uve_op_speed_enc_mode, sizeof(uve_op_speed_enc_mode)); -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel