2017-09-29 16:38 GMT+02:00 Lucas Stach <l.stach@xxxxxxxxxxxxxx>:
> The reset path wants to initialize the clock control register regardless
> of the DYNAMIC_FREQUENCY_SCALING feature, so don't call clock update, but
> explicitly load the register.
>
> Also disabling of the debug registers is moved into the reset function,
> so we always get to the same state after a GPU reset. This means the
> clock update function should not touch the bits already set in the clock
> control register, but instead only update the scaling bits.
>
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
Reviewed-by: Christian Gmeiner <christian.gmeiner@xxxxxxxxx>
> ---
> drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> index fc9a6a83dfc7..180b6a0f16ed 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> @@ -420,9 +420,10 @@ static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
> gpu->base_rate_shader >> gpu->freq_scale);
> } else {
> unsigned int fscale = 1 << (6 - gpu->freq_scale);
> - u32 clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
> - VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
> + u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
>
> + clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
> + clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
> etnaviv_gpu_load_clock(gpu, clock);
> }
> }
> @@ -445,9 +446,9 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
>
> while (time_is_after_jiffies(timeout)) {
> /* enable clock */
> - etnaviv_gpu_update_clock(gpu);
> -
> - control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
> + control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(1 << (6 -
> + gpu->freq_scale));
> + etnaviv_gpu_load_clock(gpu, control);
>
Just a little nit pick which can be ignored: add variable to make code
a tiny bit more
readable as it does not needs to code lines to assign control.
+ unsigned int fscale = 1 << (6 - gpu->freq_scale);
+ control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
+ etnaviv_gpu_load_clock(gpu, control);
> /* Wait for stable clock. Vivante's code waited for 1ms */
> usleep_range(1000, 10000);
> @@ -490,6 +491,10 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
> continue;
> }
>
> + /* disable debug registers, as they are not normally needed */
> + control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
> + gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
> +
> failed = false;
> break;
> }
> --
> 2.11.0
>
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