Comment # 5
on bug 102511
from Rob MacKinnon
Comments inline... (In reply to Alex Deucher from comment #2) > (In reply to Rob MacKinnon from comment #0) > > * Actual Result: > > - DPMS change level changes as expected. > > - Dmesg: > > [ 3302.814889] [drm:btc_dpm_set_power_state [radeon]] *ERROR* > > rv770_restrict_performance_levels_before_switch failed > > [ 3316.661933] [drm:btc_dpm_set_power_state [radeon]] *ERROR* > > rv770_restrict_performance_levels_before_switch failed > > > > * Expected result: > > - DPMS change level changes as expected. > > - No error messages in dmesg. > > Are you actually experiencing any problems? I think the error message may > be harmless can could probably be removed. The annoyance of the message is totally trivial, but I believe there is an issue with the initial setting of the DPMS profile. Which I'll mention in the next comment. > > > > * Additional Info: > > Also, not sure if this is related or not, when switching from "battery" to > > "performance" there sometimes appears to be an initial clocking issue (which > > I believe is related to #93753). Switching back and forth a few times seems > > to clean it. Unsure the cause. Another note, upon further inspection of my > > There is no real balanced state. It's either battery or performance > depending on whether the chip is on ac or dc power. The only real states > you can switch between are performance and battery. I need to see the > output of our dmesg with radeon.dpm=1 to see what states your vbios provides. I believe you when you say that the `balanced` state is non-existent. A check after cold starting shows that `balanced` is the first profile being set: # cat /sys/class/drm/card0/device/power_dpm_state balanced So I'm not sure where this profile is being set from. > > > DPMS settings, I noticed the drastic differences between "balanced" and > > "battery" `sclk`s. My understand (which could be faulty) is that `sclk` > > drives the clocking for single displays, while `mclk` for multiple. My > > sclk is the 3D engine clock. mclk is the memory clock. mclk switching is > disabled when multiple displays are active since the switch has to happen > during the display's vblank period otherwise you'd see display glitches. > With multiple displays, the vblank periods are not likely to align so mclk > switching is disabled. Thank you very much for clarifying the function of `sclk` vs `mclk`. That's great info, I wish I'd been able to find it elsewhere. My google-fu was the source of my original understanding (which as it turns out was completely wrong). Regardless, somewhere the `balanced` profile is getting pulled from with greatly under valued 3D clocking value. Is there a setting somewhere that I can trace down where this invalid profile is being generated or referenced?
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