Hi Laurent, On Thu, 2017-08-24 at 12:39 +0300, Laurent Pinchart wrote: > Hi Hean Loong, > > On Thursday, 24 August 2017 08:41:50 EEST Ong, Hean Loong wrote: > > > > Hi Laurent, > > > > I removed the examples for the HDMI in the draft below. The > > connections > > between the VIP and Display Port IP or any display connector are > > determined by HW logic. There are currently no SW defined encoders > > or > > connectors that is connected to the AVALON-ST other than the Intel > > VIP > > Frame Buffer II. Therefore there are no examples for the Display > > Port > > encoder and connector. > But there must be an encoder, even if its default configuration makes > it > usable without a softwarer driver at the moment. As the encoder is > there in > hardware, it should be described in DT. > I attach some links regarding the simple example designs for the Display Port IP The link below has a example design of how the VIP is built along with the Display Port IP into the FPGA connected to the DDR RAM accessed by ARM or any controller. Please look at the Introduction section of the link below http://www.alterawiki.com/wiki/DisplayPort_Design_Example_14.0_(RX_and_ TX)#DisplayPort_IP_Core The proposed design in the link above and the design we are implementing are almost the same (FPGA part) That the Intel(Altera) FPGA VIP is the sole interface for the ARM controller to connect to via memory mapping on the DDR Please go to Source Functional Description section in the PDF below. It has information on how the encoder is built for the FPGA design of the Display Port https://www.altera.com/ja_JP/pdfs/literature/ug/ug_displayport.pdf More information on the Display Port IP encoder could be found in the link below. The Tx Transceiver interface has some information on how the source clocks works in the FPGA tranceiver https://www.altera.com/documentation/hco1410462777019.html#hco141046232 3311 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
