On Fri, Aug 18, 2017 at 8:28 AM, Sean Paul <seanpaul@xxxxxxxxxxxx> wrote: > On Thu, Aug 17, 2017 at 12:00:04PM -0700, John Stultz wrote: >> Currently the hikey dsi logic cannot generate accurate byte >> clocks values for all pixel clock values. Thus if a mode clock >> is selected that cannot match the calculated byte clock, the >> device will boot with a blank screen. >> >> This patch uses the new mode_valid callback (many thanks to >> Jose Abreu for upstreaming it!) to ensure we don't select >> modes we cannot generate. >> >> Also, since the ade crtc code will adjust the mode in mode_set, >> this patch also adds a mode_fixup callback which we use to make >> sure we are validating the mode clock that will eventually be >> used. >> >> Cc: Daniel Vetter <daniel.vetter@xxxxxxxxx> >> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> >> Cc: Sean Paul <seanpaul@xxxxxxxxxxxx> >> Cc: David Airlie <airlied@xxxxxxxx> >> Cc: Rob Clark <robdclark@xxxxxxxxx> >> Cc: Xinliang Liu <xinliang.liu@xxxxxxxxxx> >> Cc: Xinliang Liu <z.liuxinliang@xxxxxxxxxxxxx> >> Cc: Rongrong Zou <zourongrong@xxxxxxxxx> >> Cc: Xinwei Kong <kong.kongxinwei@xxxxxxxxxxxxx> >> Cc: Chen Feng <puck.chen@xxxxxxxxxxxxx> >> Cc: Jose Abreu <Jose.Abreu@xxxxxxxxxxxx> >> Cc: Archit Taneja <architt@xxxxxxxxxxxxxx> >> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx >> Signed-off-by: John Stultz <john.stultz@xxxxxxxxxx> > > Hi John, > Thanks for continuing to send new versions for this patch. It looks good to me > (there's a small spelling mistake in a comment below that perhaps can be fixed > when applied, no biggy). > > Reviewed-by: Sean Paul <seanpaul@xxxxxxxxxxxx> Thanks so much for the review! I really appreciate it! -john _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
