Re: [PATCH] drm: rcar-du: Fix comments to comply with the kernel coding style

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On Wed, Jul 12, 2017 at 08:00:42PM +0300, Laurent Pinchart wrote:
> To avoid mixing comment styles when new comments complying with the
> kernel coding style are introduced, fix all multiline comments in one
> go.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx>

Afaik the entirety of davem's -net is commented like this, this is
checkpatch being a bit over the top. And drm is often commented like this
too.

Just fyi.
-Daniel
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.c    | 24 ++++++++++++------
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c     | 21 ++++++++++------
>  drivers/gpu/drm/rcar-du/rcar_du_group.c   | 18 ++++++++-----
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c     | 18 ++++++++-----
>  drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 12 ++++++---
>  drivers/gpu/drm/rcar-du/rcar_du_plane.c   | 42 ++++++++++++++++++++-----------
>  drivers/gpu/drm/rcar-du/rcar_du_plane.h   |  3 ++-
>  drivers/gpu/drm/rcar-du/rcar_du_vsp.c     |  6 +++--
>  8 files changed, 96 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> index f131fc68cc46..a04802f7b2f1 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> @@ -168,7 +168,8 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
>  	u32 escr;
>  	u32 div;
>  
> -	/* Compute the clock divisor and select the internal or external dot
> +	/*
> +	 * Compute the clock divisor and select the internal or external dot
>  	 * clock based on the requested frequency.
>  	 */
>  	clk = clk_get_rate(rcrtc->clock);
> @@ -261,12 +262,14 @@ void rcar_du_crtc_route_output(struct drm_crtc *crtc,
>  	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
>  	struct rcar_du_device *rcdu = rcrtc->group->dev;
>  
> -	/* Store the route from the CRTC output to the DU output. The DU will be
> +	/*
> +	 * Store the route from the CRTC output to the DU output. The DU will be
>  	 * configured when starting the CRTC.
>  	 */
>  	rcrtc->outputs |= BIT(output);
>  
> -	/* Store RGB routing to DPAD0, the hardware will be configured when
> +	/*
> +	 * Store RGB routing to DPAD0, the hardware will be configured when
>  	 * starting the CRTC.
>  	 */
>  	if (output == RCAR_DU_OUTPUT_DPAD0)
> @@ -342,7 +345,8 @@ static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
>  		}
>  	}
>  
> -	/* Update the planes to display timing and dot clock generator
> +	/*
> +	 * Update the planes to display timing and dot clock generator
>  	 * associations.
>  	 *
>  	 * Updating the DPTSR register requires restarting the CRTC group,
> @@ -450,7 +454,8 @@ static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
>  	/* Start with all planes disabled. */
>  	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
>  
> -	/* Select master sync mode. This enables display operation in master
> +	/*
> +	 * Select master sync mode. This enables display operation in master
>  	 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
>  	 * actively driven).
>  	 */
> @@ -478,7 +483,8 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
>  	if (!rcrtc->started)
>  		return;
>  
> -	/* Disable all planes and wait for the change to take effect. This is
> +	/*
> +	 * Disable all planes and wait for the change to take effect. This is
>  	 * required as the DSnPR registers are updated on vblank, and no vblank
>  	 * will occur once the CRTC is stopped. Disabling planes when starting
>  	 * the CRTC thus wouldn't be enough as it would start scanning out
> @@ -491,7 +497,8 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
>  	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
>  	drm_crtc_wait_one_vblank(crtc);
>  
> -	/* Disable vertical blanking interrupt reporting. We first need to wait
> +	/*
> +	 * Disable vertical blanking interrupt reporting. We first need to wait
>  	 * for page flip completion before stopping the CRTC as userspace
>  	 * expects page flips to eventually complete.
>  	 */
> @@ -502,7 +509,8 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
>  	if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
>  		rcar_du_vsp_disable(rcrtc);
>  
> -	/* Select switch sync mode. This stops display operation and configures
> +	/*
> +	 * Select switch sync mode. This stops display operation and configures
>  	 * the HSYNC and VSYNC signals as inputs.
>  	 */
>  	rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> index d6a0255181cc..b95437bccb3d 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> @@ -39,7 +39,8 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
>  	.features = 0,
>  	.num_crtcs = 2,
>  	.routes = {
> -		/* R8A7779 has two RGB outputs and one (currently unsupported)
> +		/*
> +		 * R8A7779 has two RGB outputs and one (currently unsupported)
>  		 * TCON output.
>  		 */
>  		[RCAR_DU_OUTPUT_DPAD0] = {
> @@ -61,7 +62,8 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
>  	.quirks = RCAR_DU_QUIRK_ALIGN_128B | RCAR_DU_QUIRK_LVDS_LANES,
>  	.num_crtcs = 3,
>  	.routes = {
> -		/* R8A7790 has one RGB output, two LVDS outputs and one
> +		/*
> +		 * R8A7790 has one RGB output, two LVDS outputs and one
>  		 * (currently unsupported) TCON output.
>  		 */
>  		[RCAR_DU_OUTPUT_DPAD0] = {
> @@ -87,7 +89,8 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
>  		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
>  	.num_crtcs = 2,
>  	.routes = {
> -		/* R8A779[13] has one RGB output, one LVDS output and one
> +		/*
> +		 * R8A779[13] has one RGB output, one LVDS output and one
>  		 * (currently unsupported) TCON output.
>  		 */
>  		[RCAR_DU_OUTPUT_DPAD0] = {
> @@ -127,7 +130,8 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
>  		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
>  	.num_crtcs = 2,
>  	.routes = {
> -		/* R8A7794 has two RGB outputs and one (currently unsupported)
> +		/*
> +		 * R8A7794 has two RGB outputs and one (currently unsupported)
>  		 * TCON output.
>  		 */
>  		[RCAR_DU_OUTPUT_DPAD0] = {
> @@ -149,7 +153,8 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
>  		  | RCAR_DU_FEATURE_VSP1_SOURCE,
>  	.num_crtcs = 4,
>  	.routes = {
> -		/* R8A7795 has one RGB output, two HDMI outputs and one
> +		/*
> +		 * R8A7795 has one RGB output, two HDMI outputs and one
>  		 * LVDS output.
>  		 */
>  		[RCAR_DU_OUTPUT_DPAD0] = {
> @@ -180,7 +185,8 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
>  		  | RCAR_DU_FEATURE_VSP1_SOURCE,
>  	.num_crtcs = 3,
>  	.routes = {
> -		/* R8A7796 has one RGB output, one LVDS output and one
> +		/*
> +		 * R8A7796 has one RGB output, one LVDS output and one
>  		 * (currently unsupported) HDMI output.
>  		 */
>  		[RCAR_DU_OUTPUT_DPAD0] = {
> @@ -341,7 +347,8 @@ static int rcar_du_probe(struct platform_device *pdev)
>  
>  	ddev->irq_enabled = 1;
>  
> -	/* Register the DRM device with the core and the connectors with
> +	/*
> +	 * Register the DRM device with the core and the connectors with
>  	 * sysfs.
>  	 */
>  	ret = drm_dev_register(ddev, 0);
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
> index 64738fca96d0..a3e29bb420fd 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
> @@ -64,7 +64,8 @@ static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
>  	if (rcdu->info->gen < 3) {
>  		defr8 |= DEFR8_DEFE8;
>  
> -		/* On Gen2 the DEFR8 register for the first group also controls
> +		/*
> +		 * On Gen2 the DEFR8 register for the first group also controls
>  		 * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for
>  		 * DU instances that support it.
>  		 */
> @@ -75,7 +76,8 @@ static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
>  				defr8 |= DEFR8_VSCS;
>  		}
>  	} else {
> -		/* On Gen3 VSPD routing can't be configured, but DPAD routing
> +		/*
> +		 * On Gen3 VSPD routing can't be configured, but DPAD routing
>  		 * needs to be set despite having a single option available.
>  		 */
>  		u32 crtc = ffs(possible_crtcs) - 1;
> @@ -124,7 +126,8 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
>  	if (rcdu->info->gen >= 3)
>  		rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);
>  
> -	/* Use DS1PR and DS2PR to configure planes priorities and connects the
> +	/*
> +	 * Use DS1PR and DS2PR to configure planes priorities and connects the
>  	 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
>  	 */
>  	rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
> @@ -177,7 +180,8 @@ static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
>  
>  void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
>  {
> -	/* Many of the configuration bits are only updated when the display
> +	/*
> +	 * Many of the configuration bits are only updated when the display
>  	 * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
>  	 * of those bits could be pre-configured, but others (especially the
>  	 * bits related to plane assignment to display timing controllers) need
> @@ -213,7 +217,8 @@ int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
>  	if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
>  		return 0;
>  
> -	/* RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
> +	/*
> +	 * RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
>  	 * configured in the DEFR8 register of the first group. As this function
>  	 * can be called with the DU0 and DU1 CRTCs disabled, we need to enable
>  	 * the first group clock before accessing the register.
> @@ -236,7 +241,8 @@ int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
>  
>  	dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
>  
> -	/* Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
> +	/*
> +	 * Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
>  	 * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
>  	 * by default.
>  	 */
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> index f4125c8ca902..91003ee13046 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> @@ -96,7 +96,8 @@ static const struct rcar_du_format_info rcar_du_format_infos[] = {
>  		.pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
>  		.edf = PnDDCR4_EDF_NONE,
>  	},
> -	/* The following formats are not supported on Gen2 and thus have no
> +	/*
> +	 * The following formats are not supported on Gen2 and thus have no
>  	 * associated .pnmr or .edf settings.
>  	 */
>  	{
> @@ -153,7 +154,8 @@ int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
>  	unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
>  	unsigned int align;
>  
> -	/* The R8A7779 DU requires a 16 pixels pitch alignment as documented,
> +	/*
> +	 * The R8A7779 DU requires a 16 pixels pitch alignment as documented,
>  	 * but the R8A7790 DU seems to require a 128 bytes pitch alignment.
>  	 */
>  	if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
> @@ -419,7 +421,8 @@ static int rcar_du_properties_init(struct rcar_du_device *rcdu)
>  	if (rcdu->props.alpha == NULL)
>  		return -ENOMEM;
>  
> -	/* The color key is expressed as an RGB888 triplet stored in a 32-bit
> +	/*
> +	 * The color key is expressed as an RGB888 triplet stored in a 32-bit
>  	 * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0)
>  	 * or enable source color keying (1).
>  	 */
> @@ -461,7 +464,8 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
>  	if (ret < 0)
>  		return ret;
>  
> -	/* Initialize vertical blanking interrupts handling. Start with vblank
> +	/*
> +	 * Initialize vertical blanking interrupts handling. Start with vblank
>  	 * disabled for all CRTCs.
>  	 */
>  	ret = drm_vblank_init(dev, (1 << rcdu->info->num_crtcs) - 1);
> @@ -481,7 +485,8 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
>  		rgrp->index = i;
>  		rgrp->num_crtcs = min(rcdu->num_crtcs - 2 * i, 2U);
>  
> -		/* If we have more than one CRTCs in this group pre-associate
> +		/*
> +		 * If we have more than one CRTCs in this group pre-associate
>  		 * the low-order planes with CRTC 0 and the high-order planes
>  		 * with CRTC 1 to minimize flicker occurring when the
>  		 * association is changed.
> @@ -537,7 +542,8 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
>  
>  	num_encoders = ret;
>  
> -	/* Set the possible CRTCs and possible clones. There's always at least
> +	/*
> +	 * Set the possible CRTCs and possible clones. There's always at least
>  	 * one way for all encoders to clone each other, set all bits in the
>  	 * possible clones field.
>  	 */
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
> index 1661f6201210..12d22f3db1af 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
> @@ -59,7 +59,8 @@ static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds,
>  
>  	rcar_lvds_write(lvds, LVDPLLCR, pllcr);
>  
> -	/* Select the input, hardcode mode 0, enable LVDS operation and turn
> +	/*
> +	 * Select the input, hardcode mode 0, enable LVDS operation and turn
>  	 * bias circuitry on.
>  	 */
>  	lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_BEN | LVDCR0_LVEN;
> @@ -73,7 +74,8 @@ static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds,
>  			LVDCR1_CHSTBY_GEN2(1) | LVDCR1_CHSTBY_GEN2(0) |
>  			LVDCR1_CLKSTBY_GEN2);
>  
> -	/* Turn the PLL on, wait for the startup delay, and turn the output
> +	/*
> +	 * Turn the PLL on, wait for the startup delay, and turn the output
>  	 * on.
>  	 */
>  	lvdcr0 |= LVDCR0_PLLON;
> @@ -140,7 +142,8 @@ static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
>  	if (ret < 0)
>  		return ret;
>  
> -	/* Hardcode the channels and control signals routing for now.
> +	/*
> +	 * Hardcode the channels and control signals routing for now.
>  	 *
>  	 * HSYNC -> CTRL0
>  	 * VSYNC -> CTRL1
> @@ -202,7 +205,8 @@ void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds,
>  {
>  	struct rcar_du_device *rcdu = lvds->dev;
>  
> -	/* The internal LVDS encoder has a restricted clock frequency operating
> +	/*
> +	 * The internal LVDS encoder has a restricted clock frequency operating
>  	 * range (30MHz to 150MHz on Gen2, 25.175MHz to 148.5MHz on Gen3). Clamp
>  	 * the clock accordingly.
>  	 */
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> index dcde6288da6c..b0040478a3db 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> @@ -57,7 +57,8 @@ static bool rcar_du_plane_needs_realloc(struct rcar_du_plane *plane,
>  
>  	cur_state = to_rcar_plane_state(plane->plane.state);
>  
> -	/* Lowering the number of planes doesn't strictly require reallocation
> +	/*
> +	 * Lowering the number of planes doesn't strictly require reallocation
>  	 * as the extra hardware plane will be freed when committing, but doing
>  	 * so could lead to more fragmentation.
>  	 */
> @@ -155,7 +156,8 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>  		dev_dbg(rcdu->dev, "%s: checking plane (%u,%tu)\n", __func__,
>  			plane->group->index, plane - plane->group->planes);
>  
> -		/* If the plane is being disabled we don't need to go through
> +		/*
> +		 * If the plane is being disabled we don't need to go through
>  		 * the full reallocation procedure. Just mark the hardware
>  		 * plane(s) as freed.
>  		 */
> @@ -168,7 +170,8 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>  			continue;
>  		}
>  
> -		/* If the plane needs to be reallocated mark it as such, and
> +		/*
> +		 * If the plane needs to be reallocated mark it as such, and
>  		 * mark the hardware plane(s) as free.
>  		 */
>  		if (rcar_du_plane_needs_realloc(plane, plane_state)) {
> @@ -186,7 +189,8 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>  	if (!needs_realloc)
>  		return 0;
>  
> -	/* Grab all plane states for the groups that need reallocation to ensure
> +	/*
> +	 * Grab all plane states for the groups that need reallocation to ensure
>  	 * locking and avoid racy updates. This serializes the update operation,
>  	 * but there's not much we can do about it as that's the hardware
>  	 * design.
> @@ -211,7 +215,8 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>  			if (IS_ERR(s))
>  				return PTR_ERR(s);
>  
> -			/* If the plane has been freed in the above loop its
> +			/*
> +			 * If the plane has been freed in the above loop its
>  			 * hardware planes must not be added to the used planes
>  			 * bitmask. However, the current state doesn't reflect
>  			 * the free state yet, as we've modified the new state
> @@ -259,14 +264,16 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>  		dev_dbg(rcdu->dev, "%s: allocating plane (%u,%tu)\n", __func__,
>  			plane->group->index, plane - plane->group->planes);
>  
> -		/* Skip planes that are being disabled or don't need to be
> +		/*
> +		 * Skip planes that are being disabled or don't need to be
>  		 * reallocated.
>  		 */
>  		if (!plane_state->format ||
>  		    !rcar_du_plane_needs_realloc(plane, plane_state))
>  			continue;
>  
> -		/* Try to allocate the plane from the free planes currently
> +		/*
> +		 * Try to allocate the plane from the free planes currently
>  		 * associated with the target CRTC to avoid restarting the CRTC
>  		 * group and thus minimize flicker. If it fails fall back to
>  		 * allocating from all free planes.
> @@ -351,14 +358,16 @@ static void rcar_du_plane_setup_scanout(struct rcar_du_group *rgrp,
>  		dma[1] = 0;
>  	}
>  
> -	/* Memory pitch (expressed in pixels). Must be doubled for interlaced
> +	/*
> +	 * Memory pitch (expressed in pixels). Must be doubled for interlaced
>  	 * operation with 32bpp formats.
>  	 */
>  	rcar_du_plane_write(rgrp, index, PnMWR,
>  			    (interlaced && state->format->bpp == 32) ?
>  			    pitch * 2 : pitch);
>  
> -	/* The Y position is expressed in raster line units and must be doubled
> +	/*
> +	 * The Y position is expressed in raster line units and must be doubled
>  	 * for 32bpp formats, according to the R8A7790 datasheet. No mention of
>  	 * doubling the Y position is found in the R8A7779 datasheet, but the
>  	 * rule seems to apply there as well.
> @@ -396,7 +405,8 @@ static void rcar_du_plane_setup_mode(struct rcar_du_group *rgrp,
>  	u32 colorkey;
>  	u32 pnmr;
>  
> -	/* The PnALPHAR register controls alpha-blending in 16bpp formats
> +	/*
> +	 * The PnALPHAR register controls alpha-blending in 16bpp formats
>  	 * (ARGB1555 and XRGB1555).
>  	 *
>  	 * For ARGB, set the alpha value to 0, and enable alpha-blending when
> @@ -413,7 +423,8 @@ static void rcar_du_plane_setup_mode(struct rcar_du_group *rgrp,
>  
>  	pnmr = PnMR_BM_MD | state->format->pnmr;
>  
> -	/* Disable color keying when requested. YUV formats have the
> +	/*
> +	 * Disable color keying when requested. YUV formats have the
>  	 * PnMR_SPIM_TP_OFF bit set in their pnmr field, disabling color keying
>  	 * automatically.
>  	 */
> @@ -457,7 +468,8 @@ static void rcar_du_plane_setup_format_gen2(struct rcar_du_group *rgrp,
>  	u32 ddcr2 = PnDDCR2_CODE;
>  	u32 ddcr4;
>  
> -	/* Data format
> +	/*
> +	 * Data format
>  	 *
>  	 * The data format is selected by the DDDF field in PnMR and the EDF
>  	 * field in DDCR4.
> @@ -589,7 +601,8 @@ static void rcar_du_plane_atomic_update(struct drm_plane *plane,
>  
>  	rcar_du_plane_setup(rplane);
>  
> -	/* Check whether the source has changed from memory to live source or
> +	/*
> +	 * Check whether the source has changed from memory to live source or
>  	 * from live source to memory. The source has been configured by the
>  	 * VSPS bit in the PnDDCR4 register. Although the datasheet states that
>  	 * the bit is updated during vertical blanking, it seems that updates
> @@ -726,7 +739,8 @@ int rcar_du_planes_init(struct rcar_du_group *rgrp)
>  	unsigned int i;
>  	int ret;
>  
> -	 /* Create one primary plane per CRTC in this group and seven overlay
> +	 /*
> +	  * Create one primary plane per CRTC in this group and seven overlay
>  	  * planes.
>  	  */
>  	rgrp->num_planes = rgrp->num_crtcs + 7;
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/rcar-du/rcar_du_plane.h
> index 8b91dd3a46e4..f62e09f195de 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.h
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.h
> @@ -20,7 +20,8 @@
>  struct rcar_du_format_info;
>  struct rcar_du_group;
>  
> -/* The RCAR DU has 8 hardware planes, shared between primary and overlay planes.
> +/*
> + * The RCAR DU has 8 hardware planes, shared between primary and overlay planes.
>   * As using overlay planes requires at least one of the CRTCs being enabled, no
>   * more than 7 overlay planes can be available. We thus create 1 primary plane
>   * per CRTC and 7 overlay planes, for a total of up to 9 KMS planes.
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> index d46dce054442..75853ce369d4 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> @@ -73,7 +73,8 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
>  
>  	__rcar_du_plane_setup(crtc->group, &state);
>  
> -	/* Ensure that the plane source configuration takes effect by requesting
> +	/*
> +	 * Ensure that the plane source configuration takes effect by requesting
>  	 * a restart of the group. See rcar_du_plane_atomic_update() for a more
>  	 * detailed explanation.
>  	 *
> @@ -417,7 +418,8 @@ int rcar_du_vsp_init(struct rcar_du_vsp *vsp)
>  	if (ret < 0)
>  		return ret;
>  
> -	 /* The VSP2D (Gen3) has 5 RPFs, but the VSP1D (Gen2) is limited to
> +	 /*
> +	  * The VSP2D (Gen3) has 5 RPFs, but the VSP1D (Gen2) is limited to
>  	  * 4 RPFs.
>  	  */
>  	vsp->num_planes = rcdu->info->gen >= 3 ? 5 : 4;
> -- 
> Regards,
> 
> Laurent Pinchart
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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