Hi Laurent,
On Wed, Jun 21, 2017 at 11:04 AM, Laurent Pinchart
<laurent.pinchart+renesas@xxxxxxxxxxxxxxxx> wrote:
> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> @@ -158,6 +157,11 @@ static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
> best_diff);
> }
>
> +static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
> + { .soc_id = "r8a7795", .revision = "ES1.*" },
> + { /* sentinel */ }
> +};
> +
> static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
> {
> const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
> @@ -185,7 +189,20 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
>
> extclk = clk_get_rate(rcrtc->extclock);
> if (rcdu->info->dpll_ch & (1 << rcrtc->index)) {
> - rcar_du_dpll_divider(rcrtc, &dpll, extclk, mode_clock);
> + unsigned long target = mode_clock;
> +
> + /*
> + * The H3 ES1.x exhibits dot clock duty cycle stability
> + * issues. We can work around them by configuring the
> + * DPLL to twice the desired frequency, coupled with a
> + * /2 post-divider. This isn't needed on other SoCs and
> + * breaks HDMI output on M3-W for a currently unknown
> + * reason, so restrict the workaround to H3 ES1.x.
> + */
> + if (soc_device_match(rcar_du_r8a7795_es1))
Matching is done over and over again, on every display enable/resume.
Can it be done at probe time?
Or in rcar_du_crtc_create(), which has access to rcrtc?
> + target *= 2;
You can also store the multiplier in rcar_du_r8a7795_es1.data
(store 1 in .data of the sentinel), removing the need for an if clause.
> +
> + rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
> extclk = dpll.output;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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