On Mon, Jun 05, 2017 at 12:01:48AM +0800, Icenowy Zheng wrote:
> + soc {
> + display_clocks: clock@1000000 {
> + compatible = "allwinner,sun8i-a83t-de2-clk";
> + reg = <0x01000000 0x100000>;
> + clocks = <&ccu CLK_BUS_DE>,
> + <&ccu CLK_DE>;
> + clock-names = "bus",
> + "mod";
> + resets = <&ccu RST_BUS_DE>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + assigned-clocks = <&ccu CLK_DE>;
> + assigned-clock-parents = <&ccu CLK_PLL_DE>;
> + assigned-clock-rates = <432000000>;
> + };
We discussed that already a few times, but there's no reason to do
so. If you need a downstream clock at a particular rate, call
clk_set_rate on it, period.
Whether its parent will be coming from PLL_DE or some other more
appriopriate clock is not relevant and doesn't make any difference.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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