于 2017年5月20日 GMT+08:00 上午2:03:30, Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> 写到: >On Thu, May 18, 2017 at 12:43:50AM +0800, Icenowy Zheng wrote: >> Allwinner H3 features a TV encoder similar to the one in earlier >SoCs, >> but with some different points about clocks: >> - It has a mod clock and a bus clock. >> - The mod clock must be at a fixed rate to generate signal. > >Why? It's experiment result by Jernej. The clock rates in BSP kernel is also specially designed (PLL_DE at 432MHz) in order to be able to feed the TVE. > >Maxime _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
