On 05/08, Eric Anholt wrote:
> This is required for the panel to work on bcm911360, where CLCDCLK is
> the fixed 200Mhz AXI41 clock. The rate set is still passed up to the
> CLCDCLK, for platforms that have a settable rate on that one.
>
> v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on
> COMMON_CLK.
>
> Signed-off-by: Eric Anholt <eric@xxxxxxxxxx>
Reviewed-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
One minor comment below
> diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c
> index 39a5c33bce7d..2d924a6bf43c 100644
> --- a/drivers/gpu/drm/pl111/pl111_display.c
> +++ b/drivers/gpu/drm/pl111/pl111_display.c
> @@ -288,6 +296,126 @@ const struct drm_simple_display_pipe_funcs pl111_display_funcs = {
[...]
> +
> + return 0;
> +}
> +
> +const struct clk_ops pl111_clk_div_ops = {
static?
> + .recalc_rate = pl111_clk_div_recalc_rate,
> + .round_rate = pl111_clk_div_round_rate,
> + .set_rate = pl111_clk_div_set_rate,
> +};
> +
> +static int
--
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a Linux Foundation Collaborative Project
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