Linus Walleij <linus.walleij@xxxxxxxxxx> writes: > On Mon, May 8, 2017 at 9:33 PM, Eric Anholt <eric@xxxxxxxxxx> wrote: > >> This is required for the panel to work on bcm911360, where CLCDCLK is >> the fixed 200Mhz AXI41 clock. The rate set is still passed up to the >> CLCDCLK, for platforms that have a settable rate on that one. >> >> v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on >> COMMON_CLK. >> >> Signed-off-by: Eric Anholt <eric@xxxxxxxxxx> > > Reviewed-by: Linus Walleij <linus.walleij@xxxxxxxxxx> Thanks. Waiting on an ack from clock folks, then we'll be ready to go, I think.
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