On Wed, 2017-05-03 at 18:16 +0200, Lucas Stach wrote: > The counter load enable bit has no effect when the shadow register > set is activated. As we always operate the PRG with shadow enabled > it is safe to remove this. > > Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > --- > drivers/gpu/ipu-v3/ipu-prg.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/ipu-v3/ipu-prg.c b/drivers/gpu/ipu-v3/ipu-prg.c > index caca57febbd6..ecc9ea44dc50 100644 > --- a/drivers/gpu/ipu-v3/ipu-prg.c > +++ b/drivers/gpu/ipu-v3/ipu-prg.c > @@ -318,8 +318,6 @@ int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan, > writel(val, prg->regs + IPU_PRG_BADDR(prg_chan)); > > val = readl(prg->regs + IPU_PRG_CTL); > - /* counter load enable */ > - val |= IPU_PRG_CTL_CNT_LOAD_EN(prg_chan); > /* config AXI ID */ > val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK << > IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan)); Applied to imx-drm/next, thanks. regards Philipp _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
