On 28/04/17 12:29 AM, Jochen Rollwagen wrote: > > 2. I’ve recently stumbled across a register definition for (older) > radeon GPU’s, what caught my eye was > > *CB:RB3D_COLORPITCH[0-3] · [R/W] · 32 bits · Access: 8/16/32 · > MMReg:0x4e38-0x4e44 * [...] > COLORENDIAN > > > > 20:19 > > > > none > > > > Specifies endian control for the color buffer > > POSSIBLE VALUES: 00 - No swap 01 - Word swap (2 bytes in 16-bit) 02 - > Dword swap (4 bytes in a 32-bit) 03 - Half-Dword swap (2 16-bit in a > 32-bit) [...] > Dumb question: Could that register be used for just setting the GPU to > big-endian mode and leave all the swapping to the GPU ? I'm afraid not, since the display hardware couldn't display the byte-swapped pixels correctly? -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
