On Fri, Apr 21, 2017 at 07:19:47PM +0200, Sylwester Nawrocki wrote: > A specific clock rate table is added for EPLL so it is possible > to set frequency of the EPLL output clock as multiple of various > audio sampling rates. > > Signed-off-by: Sylwester Nawrocki <s.nawrocki@xxxxxxxxxxx> > --- > drivers/clk/samsung/clk-exynos5420.c | 20 ++++++++++++++++++-- > 1 file changed, 18 insertions(+), 2 deletions(-) > Looks correct although I didn't check the numbers. Reviewed-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx> Best regards, Krzysztof _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
