On Mon, Apr 10, 2017 at 8:02 AM, Daniel Vetter <daniel@xxxxxxxx> wrote: > On Mon, Apr 10, 2017 at 12:12:01PM +0200, Gerd Hoffmann wrote: >> Ok, this is really a kickstart for a discussion. While working on >> graphics support for virtual machines on ppc64 (which exists in both >> little and big endian variants) I've figured the comments in the header >> file don't match reality. They are not considered little endian (as >> suggested by the comments) but in practice are used as native endian. >> >> So, go update the comments. >> >> This patch switches all 32bpp / 8 bpc formats over to native endian. >> Those used/supported by ppc64 virtual machines (virtio-gpu/bochs-drm >> drivers). >> >> Given that DRM_FORMAT_BIG_ENDIAN isn't used anywhere in the codebase >> I suspect this problem applies to more formats. When looking at >> drm_mode_legacy_fb_format it seems *all* RGB formats are actually >> native endian not little endian. >> >> Dunno where we stand in terms of YCbCr. >> >> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> Cc: Daniel Vetter <daniel.vetter@xxxxxxxxx> >> Cc: amd-gfx@xxxxxxxxxxxxxxxxxxxxx >> Signed-off-by: Gerd Hoffmann <kraxel@xxxxxxxxxx> > > I think we should go all-in on this and essentially remove the _BIG_ENDIAN > stuff. But in the end this is to be decided be the people who care about > big endian, afaik that's only you (for the pile of virt drivers we have) > and amdgpu/radeon. For radeon/amdgpu, we try to be good endian citizens when writing the code, but as far as testing and support, it's all LE. For a lot of hw blocks, the surface format is the least of your worries. Alex > -Daniel > >> --- >> include/uapi/drm/drm_fourcc.h | 16 ++++++++-------- >> 1 file changed, 8 insertions(+), 8 deletions(-) >> >> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h >> index 995c8f9..a7fc81d 100644 >> --- a/include/uapi/drm/drm_fourcc.h >> +++ b/include/uapi/drm/drm_fourcc.h >> @@ -85,15 +85,15 @@ extern "C" { >> #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ >> >> /* 32 bpp RGB */ >> -#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ >> -#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ >> -#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ >> -#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ >> +#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 native endian */ >> +#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 native endian */ >> +#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 native endian */ >> +#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 native endian */ >> >> -#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ >> -#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ >> -#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ >> -#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ >> +#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 native endian */ >> +#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 native endian */ >> +#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 native endian */ >> +#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 native endian */ >> >> #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ >> #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ >> -- >> 2.9.3 >> >> _______________________________________________ >> dri-devel mailing list >> dri-devel@xxxxxxxxxxxxxxxxxxxxx >> https://lists.freedesktop.org/mailman/listinfo/dri-devel > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel