Hi Tomi,
Thank you for the patch.
On Tuesday 28 Mar 2017 16:07:53 Tomi Valkeinen wrote:
> While implementing writeback support, odd behavior of WBDELAYCOUNT was
> observed with the combination of WB capture and HDMI. The result of the
> debugging was that the HDMI sync polarities are not set correctly.
>
> The current code sets the sync polarities going from HDMI WP to DISPC
> according to the video mode used, which seems to work normally fine, but
> causes problems with WB as WB expects the syncs to be active-high.
>
> This patch changes the HDMI sync polarities so that the DISPC always
> gets active-high syncs from HDMI WP, and the HDMI core gets sync
> polarities according to the used video mode.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@xxxxxx>
Acked-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/omapdrm/dss/hdmi_wp.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
> b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c index b783d5a0750e..597ec9d87d1d
> 100644
> --- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
> +++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
> @@ -147,15 +147,17 @@ void hdmi_wp_video_config_interface(struct
> hdmi_wp_data *wp, struct videomode *vm)
> {
> u32 r;
> - bool vsync_pol, hsync_pol;
> + bool vsync_inv, hsync_inv;
> DSSDBG("Enter hdmi_wp_video_config_interface\n");
>
> - vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH);
> - hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH);
> + vsync_inv = !!(vm->flags & DISPLAY_FLAGS_VSYNC_LOW);
> + hsync_inv = !!(vm->flags & DISPLAY_FLAGS_HSYNC_LOW);
>
> r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
> - r = FLD_MOD(r, vsync_pol, 7, 7);
> - r = FLD_MOD(r, hsync_pol, 6, 6);
> + r = FLD_MOD(r, 1, 7, 7); /* VSYNC_POL to dispc active high */
> + r = FLD_MOD(r, 1, 6, 6); /* HSYNC_POL to dispc active high */
> + r = FLD_MOD(r, vsync_inv, 5, 5); /* CORE_VSYNC_INV */
> + r = FLD_MOD(r, hsync_inv, 4, 4); /* CORE_HSYNC_INV */
> r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 3, 3);
> r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
> hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
--
Regards,
Laurent Pinchart
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