[radeon-alex:drm-next-4.12-wip 208/266] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:166:31: warning: right shift count >= width of type

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tree:   git://people.freedesktop.org/~agd5f/linux.git drm-next-4.12-wip
head:   ba92d1fc68425bbff454195c1a7bf07ec9b650d0
commit: 7b6a92ae5cf029e021246cb79c8613b19e4554d4 [208/266] drm/amdgpu: Add GMC 9.0 support (v2)
config: i386-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        git checkout 7b6a92ae5cf029e021246cb79c8613b19e4554d4
        # save the attached .config to linux build tree
        make ARCH=i386 

All warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:23:0:
   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c: In function 'gfxhub_v1_0_gart_enable':
>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:166:31: warning: right shift count >= width of type [-Wshift-count-overflow]
      (u32)(adev->dummy_page.addr >> 44));
                                  ^
   drivers/gpu/drm/amd/amdgpu/amdgpu.h:1642:53: note: in definition of macro 'WREG32'
    #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
                                                        ^
--
   In file included from drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c:23:0:
   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c: In function 'mmhub_v1_0_gart_enable':
>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c:180:31: warning: right shift count >= width of type [-Wshift-count-overflow]
      (u32)(adev->dummy_page.addr >> 44));
                                  ^
   drivers/gpu/drm/amd/amdgpu/amdgpu.h:1642:53: note: in definition of macro 'WREG32'
    #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
                                                        ^

vim +166 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

    17	 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
    18	 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
    19	 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
    20	 * OTHER DEALINGS IN THE SOFTWARE.
    21	 *
    22	 */
  > 23	#include "amdgpu.h"
    24	#include "gfxhub_v1_0.h"
    25	
    26	#include "vega10/soc15ip.h"
    27	#include "vega10/GC/gc_9_0_offset.h"
    28	#include "vega10/GC/gc_9_0_sh_mask.h"
    29	#include "vega10/GC/gc_9_0_default.h"
    30	#include "vega10/vega10_enum.h"
    31	
    32	#include "soc15_common.h"
    33	
    34	int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
    35	{
    36		u32 tmp;
    37		u64 value;
    38		u32 i;
    39	
    40		/* Program MC. */
    41		/* Update configuration */
    42		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
    43			adev->mc.vram_start >> 18);
    44		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
    45			adev->mc.vram_end >> 18);
    46	
    47		value = adev->vram_scratch.gpu_addr - adev->mc.vram_start
    48			+ adev->vm_manager.vram_base_offset;
    49		WREG32(SOC15_REG_OFFSET(GC, 0,
    50					mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),
    51					(u32)(value >> 12));
    52		WREG32(SOC15_REG_OFFSET(GC, 0,
    53					mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
    54					(u32)(value >> 44));
    55	
    56		/* Disable AGP. */
    57		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
    58		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);
    59		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF);
    60	
    61		/* GART Enable. */
    62	
    63		/* Setup TLB control */
    64		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
    65		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
    66		tmp = REG_SET_FIELD(tmp,
    67					MC_VM_MX_L1_TLB_CNTL,
    68					SYSTEM_ACCESS_MODE,
    69					3);
    70		tmp = REG_SET_FIELD(tmp,
    71					MC_VM_MX_L1_TLB_CNTL,
    72					ENABLE_ADVANCED_DRIVER_MODEL,
    73					1);
    74		tmp = REG_SET_FIELD(tmp,
    75					MC_VM_MX_L1_TLB_CNTL,
    76					SYSTEM_APERTURE_UNMAPPED_ACCESS,
    77					0);
    78		tmp = REG_SET_FIELD(tmp,
    79					MC_VM_MX_L1_TLB_CNTL,
    80					ECO_BITS,
    81					0);
    82		tmp = REG_SET_FIELD(tmp,
    83					MC_VM_MX_L1_TLB_CNTL,
    84					MTYPE,
    85					MTYPE_UC);/* XXX for emulation. */
    86		tmp = REG_SET_FIELD(tmp,
    87					MC_VM_MX_L1_TLB_CNTL,
    88					ATC_EN,
    89					1);
    90		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
    91	
    92		/* Setup L2 cache */
    93		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
    94		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
    95		tmp = REG_SET_FIELD(tmp,
    96					VM_L2_CNTL,
    97					ENABLE_L2_FRAGMENT_PROCESSING,
    98					0);
    99		tmp = REG_SET_FIELD(tmp,
   100					VM_L2_CNTL,
   101					L2_PDE0_CACHE_TAG_GENERATION_MODE,
   102					0);/* XXX for emulation, Refer to closed source code.*/
   103		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
   104		tmp = REG_SET_FIELD(tmp,
   105					VM_L2_CNTL,
   106					CONTEXT1_IDENTITY_ACCESS_MODE,
   107					1);
   108		tmp = REG_SET_FIELD(tmp,
   109					VM_L2_CNTL,
   110					IDENTITY_MODE_FRAGMENT_SIZE,
   111					0);
   112		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
   113	
   114		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));
   115		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
   116		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
   117		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp);
   118	
   119		tmp = mmVM_L2_CNTL3_DEFAULT;
   120		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);
   121	
   122		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4));
   123		tmp = REG_SET_FIELD(tmp,
   124				    VM_L2_CNTL4,
   125				    VMC_TAP_PDE_REQUEST_PHYSICAL,
   126				    0);
   127		tmp = REG_SET_FIELD(tmp,
   128				    VM_L2_CNTL4,
   129				    VMC_TAP_PTE_REQUEST_PHYSICAL,
   130				    0);
   131		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
   132	
   133		/* setup context0 */
   134		WREG32(SOC15_REG_OFFSET(GC, 0,
   135					mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
   136			(u32)(adev->mc.gtt_start >> 12));
   137		WREG32(SOC15_REG_OFFSET(GC, 0,
   138					mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
   139			(u32)(adev->mc.gtt_start >> 44));
   140	
   141		WREG32(SOC15_REG_OFFSET(GC, 0,
   142					mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
   143			(u32)(adev->mc.gtt_end >> 12));
   144		WREG32(SOC15_REG_OFFSET(GC, 0,
   145					mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
   146			(u32)(adev->mc.gtt_end >> 44));
   147	
   148		BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
   149		value = adev->gart.table_addr - adev->mc.vram_start
   150			+ adev->vm_manager.vram_base_offset;
   151		value &= 0x0000FFFFFFFFF000ULL;
   152		value |= 0x1; /*valid bit*/
   153	
   154		WREG32(SOC15_REG_OFFSET(GC, 0,
   155					mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
   156			(u32)value);
   157		WREG32(SOC15_REG_OFFSET(GC, 0,
   158					mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
   159			(u32)(value >> 32));
   160	
   161		WREG32(SOC15_REG_OFFSET(GC, 0,
   162					mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
   163			(u32)(adev->dummy_page.addr >> 12));
   164		WREG32(SOC15_REG_OFFSET(GC, 0,
   165					mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
 > 166			(u32)(adev->dummy_page.addr >> 44));
   167	
   168		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
   169		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

Attachment: .config.gz
Description: application/gzip

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