On Fri, Feb 17, 2017 at 07:28:23PM +0100, Lucas Stach wrote:
> The Prefetch Resolve Engine is a prefetch and tile resolve engine
> which prefetches display data from DRAM to an internal SRAM region.
> It has a single clock for configuration register access and the
> functional units. A single shared interrupt is used for status and
> error signaling.
>
> The only external dependency is the SRAM region to use for the
> prefetch double buffer.
>
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> ---
> .../bindings/display/imx/fsl-imx-drm.txt | 26 ++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
> index 971c3eedb1c7..1bd777d7c37d 100644
> --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
> +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
> @@ -53,6 +53,32 @@ ipu: ipu@18000000 {
> };
> };
>
> +Freescale i.MX PRE (Prefetch Resolve Engine)
> +============================================
> +
> +Required properties:
> +- compatible: should be "fsl,imx6qp-pre"
> +- reg: should be register base and length as documented in the
> + datasheet
> +- clocks : phandle to the PRE axi clock input, as described
> + in Documentation/devicetree/bindings/clock/clock-bindings.txt and
> + Documentation/devicetree/bindings/clock/imx6q-clock.txt.
> +- clock-names: should be "axi"
> +- interrupts: should contain the PRE interrupt
> +- fsl,ocram: phandle pointing to the mmio-sram device node, that should be
> + used for the PRE SRAM double buffer.
> +
> +example:
> +
> +pre@021c8000 {
Drop the leading 0.
> + compatible = "fsl,imx6qp-pre";
> + reg = <0x021c8000 0x1000>;
> + interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&clks IMX6QDL_CLK_PRE0>;
> + clock-names = "axi";
> + fsl,ocram = <&ocram2>;
> +};
> +
> Parallel display support
> ========================
>
> --
> 2.11.0
>
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