On Fri, 2017-02-17 at 21:27 +0000, Emil Velikov wrote:
> > Heh ok. I don't want to change that POST code too much as I'm not
> > equipped to test it, but I'll have a look later today.
> >
>
> Not sure why you opted for splitting each suggestion in separate
> email, but it seems to have lead to a [serious] bugfix to go
> unnoticed.
> Namely:
Dunno why either. I think I was distracted doing too many things at
once.
> > > > +static bool ddr_test_2500(struct ast_private *ast)
> > > > +{
> > > > + ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
> > > > + ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
> > > > + if (mmc_test_burst(ast, 0) < 0)
> > > > + return false;
> > > > + if (mmc_test_burst(ast, 1) < 0)
> > > > + return false;
> > > > + if (mmc_test_burst(ast, 2) < 0)
> > > > + return false;
> > > > + if (mmc_test_burst(ast, 3) < 0)
> > > > + return false;
> > > > + if (mmc_test_single_2500(ast, 0) < 0)
> > > > + return false;
> > > > + return false;
> > >
> > > Final return should be true... either things got funny with v2 or
> > > the
> > > this patch was never tested ?
As I said, never tested, I don't have the means, I'm waiting for Aspeed
to test it, hopefully monday. I can test the basic function but not
POST. I'll send a respin anyway.
Note that the POST patch is purposefully at the end of the series, it
can wait. The reason is that that code is only useful if the BMC has
no code running on it, not even u-boot, and thus its memory controller
needs to be remotely initialized by the host.
Most servers out there have something running on the BMC and all my
POWER9 systems won't boot without something on the BMC making them do
so :-)
So the POST patch can be merged later once it has had more massaging
and testing.
Cheers,
Ben.
>
> This here.
>
> Regards,
> Emil
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