On Fri, Jan 20, 2017 at 07:52:25AM +0100, Andrzej Hajda wrote: > Ultra HD modes requires clock ticking at increased rate. > > Signed-off-by: Andrzej Hajda <a.hajda@xxxxxxxxxxx> > --- > arch/arm64/boot/dts/exynos/exynos5433.dtsi | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi > index f120d99..314d928 100644 > --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi > @@ -764,6 +764,9 @@ > clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", > "aclk_xiu_decon0x", "pclk_smmu_decon0x", > "sclk_decon_vclk", "sclk_decon_eclk"; > + assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; > + assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, <0>, <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; > + assigned-clock-rates = <0>, <400000000>; Lines got too long, please split them. Best regards, Krzysztof > samsung,disp-sysreg = <&syscon_disp>; > interrupt-names = "fifo", "vsync", "lcd_sys"; > interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, > -- > 2.7.4 > _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
