On Fri, 2011-07-15 at 04:19 +0000, Matt Turner wrote: > On Wed, Jul 13, 2011 at 6:28 AM, Benjamin Herrenschmidt > <benh@xxxxxxxxxxxxxxxxxxx> wrote: > > We should have a read memory barrier between reading the WPTR from > > memory and reading ring entries based on that value (ie, we need to > > ensure both loads are done in order by the CPU). > > > > It could be argued that the MMIO reads in r600_ack_irq() might be > > enough to get that barrier but I prefer keeping an explicit one just > > in case. > > > > Signed-off-by: Benjamin Herrenschmidt <benh@xxxxxxxxxxxxxxxxxxx> > > --- > > > > (resent adding dri-devel to the CC list to hit patchwork) > > > > drivers/gpu/drm/radeon/r600.c | 3 +++ > > 1 files changed, 3 insertions(+), 0 deletions(-) > > > > diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c > > index 3c86b15..7e5c801 100644 > > --- a/drivers/gpu/drm/radeon/r600.c > > +++ b/drivers/gpu/drm/radeon/r600.c > > @@ -3312,6 +3312,9 @@ int r600_irq_process(struct radeon_device *rdev) > > } > > > > restart_ih: > > + /* Order reading of wptr vs. reading of IH ring data */ > > + wmb(); > > + > > /* display interrupts */ > > r600_irq_ack(rdev); > > The subject line says rmb(), but this says wmb(). Just want to verify > what you have is correct. Nice spotting, it's a typo and should have been rmb(). I'll fix it and respin. Cheers, Ben _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
