Comment # 13
on bug 99120
from Tom St Denis
I wonder if it's a tile mode array problem? Looking at the code for radeon/si.c and amdgpu/gfx_v6_0.c the array configs are different (entries 18-20 don't exist in the radeon side). Briefly looking at a few other entries though they seem to line up textually (assuming the defines map to the same values).
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