[Bug 98761] [regression][radeonsi][polaris]"radeonsi: set IF_THRESHOLD to 3" breaks Witcher2's ground

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Comment # 11 on bug 98761 from
First bad commit:

commit 4404d0d6e354e80dd7f8f0a0e12d8ad809cf007e
Author: Matt Arsenault <Matthew.Arsenault@amd.com>
Date:   Sun Nov 13 18:20:54 2016 +0000

    AMDGPU: Implement SGPR spilling with scalar stores

    nThis avoids the nasty problems caused by using
    memory instructions that read the exec mask while
    spilling / restoring registers used for control flow
    masking, but only for VI when these were added.

    This always uses the scalar stores when enabled currently,
    but it may be better to still try to spill to a VGPR
    and use this on the fallback memory path.

    The cache also needs to be flushed before wave termination
    if a scalar store is used.

    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286766
91177308-0d34-0410-b5e6-96231b3b80d8


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