On 11/08/2016 06:07 PM, Erik Faye-Lund wrote:
> On Tue, Nov 8, 2016 at 8:50 AM, Alexandre Courbot <acourbot@xxxxxxxxxx> wrote:
>> Add FB modifiers to allow user-space to specify that a surface is in one
>> of the two tiling formats supported by Tegra chips, and add support in
>> the tegradrm driver to handle them properly. This is necessary for the
>> display controller to directly display buffers generated by the GPU.
>>
>> This feature is intended to replace the dedicated IOCTL enabled
>> by TEGRA_STAGING and to provide a non-staging alternative to that
>> solution.
>>
>> Signed-off-by: Alexandre Courbot <acourbot@xxxxxxxxxx>
>> ---
>> drivers/gpu/drm/tegra/drm.c | 2 ++
>> drivers/gpu/drm/tegra/fb.c | 23 +++++++++++++++++++---
>> include/uapi/drm/drm_fourcc.h | 45 +++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 67 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
>> index a9630c2d6cb3..36b4b30a5164 100644
>> --- a/drivers/gpu/drm/tegra/drm.c
>> +++ b/drivers/gpu/drm/tegra/drm.c
>> @@ -161,6 +161,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
>> drm->mode_config.max_width = 4096;
>> drm->mode_config.max_height = 4096;
>>
>> + drm->mode_config.allow_fb_modifiers = true;
>> +
>> drm->mode_config.funcs = &tegra_drm_mode_funcs;
>>
>> err = tegra_drm_fb_prepare(drm);
>> diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c
>> index e6d71fa4028e..2fded58b2ca5 100644
>> --- a/drivers/gpu/drm/tegra/fb.c
>> +++ b/drivers/gpu/drm/tegra/fb.c
>> @@ -52,9 +52,26 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
>> struct tegra_bo_tiling *tiling)
>> {
>> struct tegra_fb *fb = to_tegra_fb(framebuffer);
>> -
>> - /* TODO: handle YUV formats? */
>> - *tiling = fb->planes[0]->tiling;
>> + uint64_t modifier = fb->base.modifier[0];
>> +
>> + switch (fourcc_mod_tegra_mod(modifier)) {
>> + case NV_FORMAT_MOD_TEGRA_TILED:
>> + tiling->mode = TEGRA_BO_TILING_MODE_TILED;
>> + tiling->value = 0;
>> + break;
>> +
>> + case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0):
>> + tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
>> + tiling->value = fourcc_mod_tegra_param(modifier);
>> + if (tiling->value > 5)
>> + return -EINVAL;
>
> Shouldn't this contain some hardware-check for the support? AFAIK, not
> all Tegras support all block-heights (if even this mode at all?)...
tegra_dc_setup_window does that check later (check the test on
dc->soc->supports_block_linear). At the moment no error message is
displayed though (and it seems like we are writing a stale value in
DC_WIN_BUFFER_ADDR_MODE if the SoC doesn't support block linear and the
tiling mode is TEGRA_BO_TILING_MODE_BLOCK?)
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