Comment # 2
on bug 98352
from Ville Syrjala
The problem on this machine seems to be that the clock is about .6% off, whereas the test will accept a deviation up to .5%. I also have a VLV machine with DSI that suffers from a similar problem. I think for internal panels the best solution might be for the kernel to fix up the reported clock for the fixed mode. Not sure what we'd do about the EDID though, assuming the the panel has one and the difference in the clocks would be large enough to be visible in the EDID timings. And of course not all modes coming from the EDID even have actual detailed timing descriptors.
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