2016-09-29 9:55 GMT+02:00 Jyri Sarha <jsarha@xxxxxx>: > On 09/28/16 15:41, Bartosz Golaszewski wrote: >> Some architectures don't use the common clock framework and don't >> implement all the clk interfaces for every clock. This is the case >> for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1. >> >> Trying to set the clock rate for the LCDC clock results in -EINVAL >> being returned. >> >> As a workaround for that: if the call to clk_set_rate() fails, fall >> back to adjusting the clock divider instead. Proper divider value is >> calculated by dividing the current clock rate by the required pixel >> clock rate in HZ. >> >> This code is based on a hack initially developed internally for >> baylibre by Karl Beldan <kbeldan@xxxxxxxxxxxx>. >> >> Tested with a da850-lcdk with an LCD display connected over VGA. >> >> Signed-off-by: Bartosz Golaszewski <bgolaszewski@xxxxxxxxxxxx> > > I'd say that a warn with backtrace over kill here (we know quite well > how we end up here). And it would be helpful to know in actual numbers > what the clock should have been and how close to it did we get. > > Otherwise the patch appears to work fine at least on am335x. > Actually there's one more issue - the requested clock rate is in crtc->mode.clock, not in the rate variable, so that needs fixing too for the message to be correct. Best regards, Bartosz Golaszewski _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
