This series is,
Reviewed-by: Edward O'Callaghan <funfunctor@xxxxxxxxxxxxxxxx>
On 09/25/2016 06:19 PM, Baoyou Xie wrote:
> We get a few warnings when building kernel with W=1:
> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_hwmgr.c:69:10: warning: no previous prototype for 'cz_get_eclk_level' [-Wmissing-prototypes]
> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/tonga_hwmgr.c:117:27: warning: no previous prototype for 'cast_phw_tonga_power_state' [-Wmissing-prototypes]
> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/tonga_thermal.c:363:5: warning: no previous prototype for 'tf_tonga_thermal_setup_fan_table' [-Wmissing-prototypes]
> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/iceland_hwmgr.c:139:5: warning: no previous prototype for 'iceland_get_memory_type' [-Wmissing-prototypes]
> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/iceland_thermal.c:363:5: warning: no previous prototype for 'tf_iceland_thermal_setup_fan_table' [-Wmissing-prototypes]
> ....
>
> In fact, these functions are only used in the file in which they are
> declared and don't need a declaration, but can be made static.
> So this patch marks these functions with 'static'.
>
> Signed-off-by: Baoyou Xie <baoyou.xie@xxxxxxxxxx>
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 12 +-
> .../gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c | 86 +++++++------
> .../gpu/drm/amd/powerplay/hwmgr/iceland_thermal.c | 10 +-
> .../amd/powerplay/hwmgr/process_pptables_v1_0.c | 6 +-
> .../gpu/drm/amd/powerplay/hwmgr/processpptables.c | 4 +-
> .../amd/powerplay/hwmgr/tonga_clockpowergating.c | 4 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 140 +++++++++++----------
> .../gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c | 9 +-
> drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 22 ++--
> .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 2 +-
> .../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 22 ++--
> .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 2 +-
> 13 files changed, 179 insertions(+), 146 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index b1d1940..83a355c 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -507,7 +507,9 @@ static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
> }
> }
>
> -int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
> +static int
> +pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id,
> + void *input, void *output)
> {
> int ret = 0;
> struct pp_instance *pp_handle;
> @@ -546,7 +548,7 @@ int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input,
> return ret;
> }
>
> -enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
> +static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
> {
> struct pp_hwmgr *hwmgr;
> struct pp_power_state *state;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index 5ecef17..41dfc34 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -66,7 +66,7 @@ static const struct cz_power_state *cast_const_PhwCzPowerState(
> return (struct cz_power_state *)hw_ps;
> }
>
> -uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
> +static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
> uint32_t clock, uint32_t msg)
> {
> int i = 0;
> @@ -1017,7 +1017,7 @@ static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
> return 0;
> }
>
> -int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
> +static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
> void *output, void *storage, int result)
> {
> struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
> @@ -1225,7 +1225,7 @@ static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
> +static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
> {
> struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>
> @@ -1239,7 +1239,7 @@ int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
> +static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
> {
> struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
> struct phm_clock_voltage_dependency_table *table =
> @@ -1277,7 +1277,7 @@ int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
> +static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
> {
> struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>
> @@ -1533,7 +1533,7 @@ static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
> return result;
> }
>
> -int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
> +static int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
> {
> return sizeof(struct cz_power_state);
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
> index 5abe433..364c846 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
> @@ -136,7 +136,7 @@ static int iceland_read_clock_registers(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int iceland_get_memory_type(struct pp_hwmgr *hwmgr)
> +static int iceland_get_memory_type(struct pp_hwmgr *hwmgr)
> {
> iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
> uint32_t temp;
> @@ -162,7 +162,7 @@ int iceland_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int iceland_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
> +static int iceland_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
> {
> PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1);
>
> @@ -175,7 +175,7 @@ int iceland_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int iceland_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
> +static int iceland_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
> {
> cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
>
> @@ -262,7 +262,7 @@ static void iceland_trim_voltage_table_to_fit_state_table(
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int iceland_enable_voltage_control(struct pp_hwmgr *hwmgr)
> +static int iceland_enable_voltage_control(struct pp_hwmgr *hwmgr)
> {
> /* enable voltage control */
> PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
> @@ -298,7 +298,7 @@ static int iceland_get_svi2_voltage_table(struct pp_hwmgr *hwmgr,
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int iceland_construct_voltage_tables(struct pp_hwmgr *hwmgr)
> +static int iceland_construct_voltage_tables(struct pp_hwmgr *hwmgr)
> {
> iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
> int result;
> @@ -380,12 +380,12 @@ int iceland_construct_voltage_tables(struct pp_hwmgr *hwmgr)
>
> /*---------------------------MC----------------------------*/
>
> -uint8_t iceland_get_memory_module_index(struct pp_hwmgr *hwmgr)
> +static uint8_t iceland_get_memory_module_index(struct pp_hwmgr *hwmgr)
> {
> return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
> }
>
> -bool iceland_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
> +static bool iceland_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
> {
> bool result = true;
>
> @@ -478,7 +478,7 @@ bool iceland_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
> return result;
> }
>
> -int iceland_set_s0_mc_reg_index(phw_iceland_mc_reg_table *table)
> +static int iceland_set_s0_mc_reg_index(phw_iceland_mc_reg_table *table)
> {
> uint32_t i;
> uint16_t address;
> @@ -491,7 +491,9 @@ int iceland_set_s0_mc_reg_index(phw_iceland_mc_reg_table *table)
> return 0;
> }
>
> -int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_iceland_mc_reg_table *ni_table)
> +static int
> +iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
> + phw_iceland_mc_reg_table *ni_table)
> {
> uint8_t i, j;
>
> @@ -690,7 +692,8 @@ static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int iceland_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
> +static int
> +iceland_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
> {
> iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
>
> @@ -712,7 +715,7 @@ int iceland_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int iceland_enable_display_gap(struct pp_hwmgr *hwmgr)
> +static int iceland_enable_display_gap(struct pp_hwmgr *hwmgr)
> {
> uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
> CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
> @@ -735,7 +738,7 @@ int iceland_enable_display_gap(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int iceland_program_voting_clients(struct pp_hwmgr *hwmgr)
> +static int iceland_program_voting_clients(struct pp_hwmgr *hwmgr)
> {
> iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
>
> @@ -873,7 +876,7 @@ static int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
> * Copy one arb setting to another and then switch the active set.
> * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants.
> */
> -int iceland_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
> +static int iceland_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
> uint32_t arbFreqSrc, uint32_t arbFreqDest)
> {
> uint32_t mc_arb_dram_timing;
> @@ -930,7 +933,7 @@ int iceland_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
> * @return always 0
> * This function is to be called from the SetPowerState table.
> */
> -int iceland_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
> +static int iceland_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
> {
> return iceland_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
> }
> @@ -1406,7 +1409,7 @@ int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr)
> * @return always 0
> */
>
> -int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
> +static int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
> SMU71_Discrete_DpmTable *table)
> {
> int result;
> @@ -1448,7 +1451,7 @@ static uint32_t iceland_get_dpm_level_enable_mask_value(
> return mask_value;
> }
>
> -int iceland_populate_memory_timing_parameters(
> +static int iceland_populate_memory_timing_parameters(
> struct pp_hwmgr *hwmgr,
> uint32_t engine_clock,
> uint32_t memory_clock,
> @@ -1484,7 +1487,7 @@ int iceland_populate_memory_timing_parameters(
> * @return always 0
> * This function is to be called from the SetPowerState table.
> */
> -int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
> +static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
> {
> iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
> int result = 0;
> @@ -2006,7 +2009,8 @@ static int iceland_populate_single_memory_level(
> * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
> * @param voltage the SMC VOLTAGE structure to be populated
> */
> -int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMU71_Discrete_VoltageLevel *voltage)
> +static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
> + SMU71_Discrete_VoltageLevel *voltage)
> {
> const iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
> uint32_t i = 0;
> @@ -2185,7 +2189,7 @@ static int iceland_find_boot_level(struct iceland_single_dpm_table *table, uint3
> * @param engine_clock the engine clock to use to populate the structure
> * @param sclk the SMC SCLK structure to be populated
> */
> -int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr,
> +static int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr,
> uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk)
> {
> const iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
> @@ -2783,7 +2787,8 @@ static int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
> return result;
> }
>
> -int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU71_Discrete_MCRegisters *mc_reg_table)
> +static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
> + SMU71_Discrete_MCRegisters *mc_reg_table)
> {
> const struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
>
> @@ -2807,7 +2812,7 @@ int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU71_Discrete_MCReg
> }
>
> /* convert register values from driver to SMC format */
> -void iceland_convert_mc_registers(
> +static void iceland_convert_mc_registers(
> const phw_iceland_mc_reg_entry * pEntry,
> SMU71_Discrete_MCRegisterSet *pData,
> uint32_t numEntries, uint32_t validflag)
> @@ -2823,7 +2828,7 @@ void iceland_convert_mc_registers(
> }
>
> /* find the entry in the memory range table, then populate the value to SMC's iceland_mc_reg_table */
> -int iceland_convert_mc_reg_table_entry_to_smc(
> +static int iceland_convert_mc_reg_table_entry_to_smc(
> struct pp_hwmgr *hwmgr,
> const uint32_t memory_clock,
> SMU71_Discrete_MCRegisterSet *mc_reg_table_data
> @@ -2848,7 +2853,7 @@ int iceland_convert_mc_reg_table_entry_to_smc(
> return 0;
> }
>
> -int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
> +static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
> SMU71_Discrete_MCRegisters *mc_reg_table)
> {
> int result = 0;
> @@ -2870,7 +2875,7 @@ int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
> return result;
> }
>
> -int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
> +static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
> {
> int result;
> struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
> @@ -2888,21 +2893,22 @@ int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
> (uint8_t *)&data->mc_reg_table, sizeof(SMU71_Discrete_MCRegisters), data->sram_end);
> }
>
> -int iceland_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
> +static int
> +iceland_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
> {
> PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
>
> return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
> }
>
> -int iceland_enable_sclk_control(struct pp_hwmgr *hwmgr)
> +static int iceland_enable_sclk_control(struct pp_hwmgr *hwmgr)
> {
> PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0);
>
> return 0;
> }
>
> -int iceland_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
> +static int iceland_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
> {
> iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
>
> @@ -2946,7 +2952,7 @@ int iceland_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int iceland_start_dpm(struct pp_hwmgr *hwmgr)
> +static int iceland_start_dpm(struct pp_hwmgr *hwmgr)
> {
> iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
>
> @@ -3897,7 +3903,7 @@ static int iceland_get_num_of_entries(struct pp_hwmgr *hwmgr)
>
> static const unsigned long PhwIceland_Magic = (unsigned long)(PHM_VIslands_Magic);
>
> -struct iceland_power_state *cast_phw_iceland_power_state(
> +static struct iceland_power_state *cast_phw_iceland_power_state(
> struct pp_hw_power_state *hw_ps)
> {
> if (hw_ps == NULL)
> @@ -4069,7 +4075,7 @@ static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
> * @param n : DPM level
> * @return The response that came from the SMC.
> */
> -int iceland_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
> +static int iceland_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
> {
> iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
>
> @@ -4092,7 +4098,7 @@ int iceland_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
> * @param n : DPM level
> * @return The response that came from the SMC.
> */
> -int iceland_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
> +static int iceland_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
> {
> iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
>
> @@ -4115,7 +4121,7 @@ int iceland_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
> * @param n : DPM level
> * @return The response that came from the SMC.
> */
> -int iceland_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
> +static int iceland_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
> {
> iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
>
> @@ -4221,7 +4227,7 @@ static int iceland_force_dpm_lowest(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int iceland_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
> +static int iceland_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
> {
> iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
>
> @@ -4285,7 +4291,7 @@ static int iceland_force_dpm_level(struct pp_hwmgr *hwmgr,
> return ret;
> }
>
> -const struct iceland_power_state *cast_const_phw_iceland_power_state(
> +static const struct iceland_power_state *cast_const_phw_iceland_power_state(
> const struct pp_hw_power_state *hw_ps)
> {
> if (hw_ps == NULL)
> @@ -4761,7 +4767,7 @@ static int iceland_notify_link_speed_change_after_state_change(struct pp_hwmgr *
> return 0;
> }
>
> -int iceland_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
> +static int iceland_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
> {
> PPSMC_Result result;
> iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
> @@ -5134,7 +5140,8 @@ iceland_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
> seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
> }
>
> -int iceland_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
> +static int
> +iceland_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
> {
> uint32_t num_active_displays = 0;
> struct cgs_display_info info = {0};
> @@ -5158,7 +5165,7 @@ int iceland_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always OK
> */
> -int iceland_program_display_gap(struct pp_hwmgr *hwmgr)
> +static int iceland_program_display_gap(struct pp_hwmgr *hwmgr)
> {
> uint32_t num_active_displays = 0;
> uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
> @@ -5201,7 +5208,7 @@ int iceland_program_display_gap(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int iceland_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
> +static int iceland_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
> {
> iceland_program_display_gap(hwmgr);
>
> @@ -5339,7 +5346,8 @@ static inline bool iceland_are_power_levels_equal(const struct iceland_performan
> (pl1->pcie_lane == pl2->pcie_lane));
> }
>
> -int iceland_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1,
> +static int iceland_check_states_equal(struct pp_hwmgr *hwmgr,
> + const struct pp_hw_power_state *pstate1,
> const struct pp_hw_power_state *pstate2, bool *equal)
> {
> const struct iceland_power_state *psa = cast_const_phw_iceland_power_state(pstate1);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_thermal.c
> index 527f370..9b90d1f 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_thermal.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_thermal.c
> @@ -150,7 +150,7 @@ static int iceland_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int iceland_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
> +static int iceland_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
> {
> return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl) == 0) ? 0 : -EINVAL;
> }
> @@ -360,7 +360,9 @@ int iceland_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
> * @param Result the last failure code
> * @return result from set temperature range routine
> */
> -int tf_iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result)
> +static int
> +tf_iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input,
> + void *output, void *storage, int result)
> {
> struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
> SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
> @@ -451,7 +453,9 @@ int tf_iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, void
> * @param Result the last failure code
> * @return result from set temperature range routine
> */
> -int tf_iceland_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result)
> +static int
> +tf_iceland_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, void *input,
> + void *output, void *storage, int result)
> {
> /* If the fantable setup has failed we could have disabled PHM_PlatformCaps_MicrocodeFanControl even after this function was included in the table.
> * Make sure that we still think controlling the fan is OK.
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> index 7de701d..155cd0d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> @@ -131,7 +131,7 @@ static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
> /**
> * Private Function to get the PowerPlay Table Address.
> */
> -const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
> +static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
> {
> int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
>
> @@ -1049,7 +1049,7 @@ static int check_powerplay_tables(
> return 0;
> }
>
> -int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
> +static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
> {
> int result = 0;
> const ATOM_Tonga_POWERPLAYTABLE *powerplay_table;
> @@ -1100,7 +1100,7 @@ int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
> return result;
> }
>
> -int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
> +static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
> {
> struct phm_ppt_v1_information *pp_table_information =
> (struct phm_ppt_v1_information *)(hwmgr->pptable);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> index ccf7ebe..bd1f190 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> @@ -1507,7 +1507,7 @@ static int init_phase_shedding_table(struct pp_hwmgr *hwmgr,
> return 0;
> }
>
> -int get_number_of_vce_state_table_entries(
> +static int get_number_of_vce_state_table_entries(
> struct pp_hwmgr *hwmgr)
> {
> const ATOM_PPLIB_POWERPLAYTABLE *table =
> @@ -1521,7 +1521,7 @@ int get_number_of_vce_state_table_entries(
> return 0;
> }
>
> -int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
> +static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
> unsigned long i,
> struct pp_vce_state *vce_state,
> void **clock_info,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c
> index e58d038..c1a717c 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c
> @@ -34,7 +34,7 @@ int tonga_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int tonga_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
> +static int tonga_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
> {
> if (phm_cf_want_uvd_power_gating(hwmgr)) {
> if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> @@ -58,7 +58,7 @@ int tonga_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int tonga_phm_powerup_vce(struct pp_hwmgr *hwmgr)
> +static int tonga_phm_powerup_vce(struct pp_hwmgr *hwmgr)
> {
> if (phm_cf_want_vce_power_gating(hwmgr))
> return smum_send_msg_to_smc(hwmgr->smumgr,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
> index 582d04a..667bb0e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
> @@ -114,7 +114,7 @@ typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
>
> static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
>
> -struct tonga_power_state *cast_phw_tonga_power_state(
> +static struct tonga_power_state *cast_phw_tonga_power_state(
> struct pp_hw_power_state *hw_ps)
> {
> if (hw_ps == NULL)
> @@ -127,7 +127,7 @@ struct tonga_power_state *cast_phw_tonga_power_state(
> return (struct tonga_power_state *)hw_ps;
> }
>
> -const struct tonga_power_state *cast_const_phw_tonga_power_state(
> +static const struct tonga_power_state *cast_const_phw_tonga_power_state(
> const struct pp_hw_power_state *hw_ps)
> {
> if (hw_ps == NULL)
> @@ -140,7 +140,7 @@ const struct tonga_power_state *cast_const_phw_tonga_power_state(
> return (const struct tonga_power_state *)hw_ps;
> }
>
> -int tonga_add_voltage(struct pp_hwmgr *hwmgr,
> +static int tonga_add_voltage(struct pp_hwmgr *hwmgr,
> phm_ppt_v1_voltage_lookup_table *look_up_table,
> phm_ppt_v1_voltage_lookup_record *record)
> {
> @@ -181,7 +181,7 @@ int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
> return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
> }
>
> -uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
> +static uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
> uint32_t voltage)
> {
> uint8_t count = (uint8_t) (voltage_table->count);
> @@ -211,7 +211,8 @@ uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
> * @param voltage - voltage to look for
> * @return 0 on success
> */
> -uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
> +static uint8_t
> +tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
> uint16_t voltage)
> {
> uint8_t count = (uint8_t) (look_up_table->count);
> @@ -268,7 +269,7 @@ static uint32_t tonga_get_dpm_level_enable_mask_value(
> *
> * @param hwmgr the address of the powerplay hardware manager.
> */
> -void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
> +static void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> phw_tonga_ulv_parm *ulv = &(data->ulv);
> @@ -405,7 +406,7 @@ static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
> * @param hwmgr the address of the powerplay hardware manager.
> * @return 2 if vddgfx returned is greater than 2V or if BIOS
> */
> -int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
> +static int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
> @@ -477,7 +478,7 @@ int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
> +static int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
>
> @@ -521,7 +522,7 @@ int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int tonga_start_dpm(struct pp_hwmgr *hwmgr)
> +static int tonga_start_dpm(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
>
> @@ -565,7 +566,7 @@ int tonga_start_dpm(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
> +static int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
>
> @@ -604,7 +605,7 @@ int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
> +static int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
>
> @@ -646,7 +647,7 @@ int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr)
> +static int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr)
> {
> PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0);
>
> @@ -684,7 +685,7 @@ PPSMC_Result tonga_send_msg_to_smc_return_parameter(
> * @param n : DPM level
> * @return The response that came from the SMC.
> */
> -int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
> +static int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> uint32_t level_mask = 1 << n;
> @@ -709,7 +710,7 @@ int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
> * @param n : DPM level
> * @return The response that came from the SMC.
> */
> -int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
> +static int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> uint32_t level_mask = 1 << n;
> @@ -734,7 +735,7 @@ int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
> * @param n : DPM level
> * @return The response that came from the SMC.
> */
> -int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
> +static int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
>
> @@ -757,7 +758,7 @@ int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_set_boot_state(struct pp_hwmgr *hwmgr)
> +static int tonga_set_boot_state(struct pp_hwmgr *hwmgr)
> {
> /*
> * SMC only stores one state that SW will ask to switch too,
> @@ -857,7 +858,7 @@ static int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_read_clock_registers(struct pp_hwmgr *hwmgr)
> +static int tonga_read_clock_registers(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
>
> @@ -901,7 +902,7 @@ int tonga_read_clock_registers(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_get_memory_type(struct pp_hwmgr *hwmgr)
> +static int tonga_get_memory_type(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> uint32_t temp;
> @@ -921,7 +922,7 @@ int tonga_get_memory_type(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
> +static int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
> {
> PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1);
>
> @@ -934,7 +935,7 @@ int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
> +static int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
>
> @@ -953,7 +954,7 @@ int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
> +static int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
> {
> /*
> * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
> @@ -969,7 +970,7 @@ int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr)
> +static int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
>
> @@ -1123,7 +1124,7 @@ static void tonga_trim_voltage_table_to_fit_state_table(
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr)
> +static int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
> @@ -1385,7 +1386,7 @@ static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
> * @return always 0
> */
>
> -int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
> +static int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
> SMU72_Discrete_DpmTable *table)
> {
> int result;
> @@ -1530,12 +1531,12 @@ static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_reset_to_default(struct pp_hwmgr *hwmgr)
> +static int tonga_reset_to_default(struct pp_hwmgr *hwmgr)
> {
> return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1;
> }
>
> -int tonga_populate_memory_timing_parameters(
> +static int tonga_populate_memory_timing_parameters(
> struct pp_hwmgr *hwmgr,
> uint32_t engine_clock,
> uint32_t memory_clock,
> @@ -1571,7 +1572,7 @@ int tonga_populate_memory_timing_parameters(
> * @return always 0
> * This function is to be called from the SetPowerState table.
> */
> -int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
> +static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> int result = 0;
> @@ -2109,7 +2110,8 @@ static int tonga_populate_single_memory_level(
> * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
> * @param voltage the SMC VOLTAGE structure to be populated
> */
> -int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern)
> +static int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
> + SMIO_Pattern *smio_pattern)
> {
> const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
> @@ -2333,7 +2335,7 @@ static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
> * @param engine_clock the engine clock to use to populate the structure
> * @param sclk the SMC SCLK structure to be populated
> */
> -int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
> +static int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
> uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
> {
> const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> @@ -3123,7 +3125,7 @@ static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
> return;
> }
>
> -int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
> +static int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
> {
> PPSMC_Result result;
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> @@ -3165,7 +3167,7 @@ int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
> }
>
>
> -int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr)
> +static int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr)
> {
> uint32_t level, tmp;
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> @@ -3329,7 +3331,7 @@ static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
> +static int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> int result = 1;
> @@ -3590,7 +3592,7 @@ static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage(
> return 0;
> }
>
> -int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr,
> +static int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr,
> phm_ppt_v1_voltage_lookup_table *lookup_table)
> {
> uint32_t table_size, i, j;
> @@ -3666,7 +3668,7 @@ static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr)
> return result;
> }
>
> -int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr)
> +static int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
> data->low_sclk_interrupt_threshold = 0;
> @@ -3674,7 +3676,7 @@ int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int tonga_setup_asic_task(struct pp_hwmgr *hwmgr)
> +static int tonga_setup_asic_task(struct pp_hwmgr *hwmgr)
> {
> int tmp_result, result = 0;
>
> @@ -3711,7 +3713,7 @@ int tonga_setup_asic_task(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr)
> +static int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr)
> {
> /* enable voltage control */
> PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
> @@ -3724,7 +3726,7 @@ int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr)
> *
> * @param hwmgr the address of the powerplay hardware manager.
> */
> -bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr)
> +static bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr)
> {
> const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
>
> @@ -3733,12 +3735,12 @@ bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr)
>
> /*---------------------------MC----------------------------*/
>
> -uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
> +static uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
> {
> return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
> }
>
> -bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
> +static bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
> {
> bool result = true;
>
> @@ -3831,7 +3833,7 @@ bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
> return result;
> }
>
> -int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table)
> +static int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table)
> {
> uint32_t i;
> uint16_t address;
> @@ -3844,7 +3846,9 @@ int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table)
> return 0;
> }
>
> -int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table)
> +static int
> +tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
> + phw_tonga_mc_reg_table *ni_table)
> {
> uint8_t i, j;
>
> @@ -3883,7 +3887,8 @@ int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_to
> * @param table the address of MCRegTable
> * @return always 0
> */
> -int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table)
> +static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr,
> + phw_tonga_mc_reg_table *table)
> {
> uint8_t i, j, k;
> uint32_t temp_reg;
> @@ -3965,7 +3970,7 @@ int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_tabl
> return 0;
> }
>
> -int tonga_set_valid_flag(phw_tonga_mc_reg_table *table)
> +static int tonga_set_valid_flag(phw_tonga_mc_reg_table *table)
> {
> uint8_t i, j;
> for (i = 0; i < table->last; i++) {
> @@ -4039,7 +4044,7 @@ static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
> * Copy one arb setting to another and then switch the active set.
> * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants.
> */
> -int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
> +static int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
> uint32_t arbFreqSrc, uint32_t arbFreqDest)
> {
> uint32_t mc_arb_dram_timing;
> @@ -4096,7 +4101,7 @@ int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
> * @return always 0
> * This function is to be called from the SetPowerState table.
> */
> -int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
> +static int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
> {
> return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
> }
> @@ -4107,7 +4112,7 @@ int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
> +static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
> {
> const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
> uint32_t tmp;
> @@ -4132,7 +4137,8 @@ int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
> data->arb_table_start, tmp, data->sram_end);
> }
>
> -int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table)
> +static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
> + SMU72_Discrete_MCRegisters *mc_reg_table)
> {
> const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
>
> @@ -4156,7 +4162,7 @@ int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegis
> }
>
> /*convert register values from driver to SMC format */
> -void tonga_convert_mc_registers(
> +static void tonga_convert_mc_registers(
> const phw_tonga_mc_reg_entry * pEntry,
> SMU72_Discrete_MCRegisterSet *pData,
> uint32_t numEntries, uint32_t validflag)
> @@ -4172,7 +4178,7 @@ void tonga_convert_mc_registers(
> }
>
> /* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */
> -int tonga_convert_mc_reg_table_entry_to_smc(
> +static int tonga_convert_mc_reg_table_entry_to_smc(
> struct pp_hwmgr *hwmgr,
> const uint32_t memory_clock,
> SMU72_Discrete_MCRegisterSet *mc_reg_table_data
> @@ -4197,7 +4203,7 @@ int tonga_convert_mc_reg_table_entry_to_smc(
> return 0;
> }
>
> -int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
> +static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
> SMU72_Discrete_MCRegisters *mc_reg_table)
> {
> int result = 0;
> @@ -4219,7 +4225,7 @@ int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
> return result;
> }
>
> -int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
> +static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
> {
> int result;
> struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
> @@ -4243,7 +4249,8 @@ int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
> +static int
> +tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
>
> @@ -4265,7 +4272,7 @@ int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_enable_display_gap(struct pp_hwmgr *hwmgr)
> +static int tonga_enable_display_gap(struct pp_hwmgr *hwmgr)
> {
> uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
> CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
> @@ -4288,7 +4295,7 @@ int tonga_enable_display_gap(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always 0
> */
> -int tonga_program_voting_clients(struct pp_hwmgr *hwmgr)
> +static int tonga_program_voting_clients(struct pp_hwmgr *hwmgr)
> {
> tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
>
> @@ -4392,7 +4399,7 @@ static int tonga_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
> return tonga_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
> }
>
> -int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
> +static int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
> {
> int tmp_result, result = 0;
>
> @@ -4481,7 +4488,7 @@ int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
> return result;
> }
>
> -int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
> +static int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
> {
> int tmp_result, result = 0;
>
> @@ -4515,7 +4522,7 @@ int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr)
> return result;
> }
>
> -int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
> +static int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
> {
> return phm_hwmgr_backend_fini(hwmgr);
> }
> @@ -4526,7 +4533,7 @@ int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return 1 if success; otherwise appropriate error code.
> */
> -int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
> +static int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
> {
> int result = 0;
> SMU72_Discrete_DpmTable *table = NULL;
> @@ -4930,7 +4937,7 @@ static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
> return 0;
> }
>
> -int tonga_get_power_state_size(struct pp_hwmgr *hwmgr)
> +static int tonga_get_power_state_size(struct pp_hwmgr *hwmgr)
> {
> return sizeof(struct tonga_power_state);
> }
> @@ -5869,7 +5876,7 @@ int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
> * @param hwmgr the address of the powerplay hardware manager.
> * @return always OK
> */
> -int tonga_program_display_gap(struct pp_hwmgr *hwmgr)
> +static int tonga_program_display_gap(struct pp_hwmgr *hwmgr)
> {
> struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
> uint32_t num_active_displays = 0;
> @@ -5913,7 +5920,7 @@ int tonga_program_display_gap(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
> +static int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
> {
>
> tonga_program_display_gap(hwmgr);
> @@ -5971,7 +5978,7 @@ uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr)
> return reference_clock;
> }
>
> -int tonga_dpm_set_interrupt_state(void *private_data,
> +static int tonga_dpm_set_interrupt_state(void *private_data,
> unsigned src_id, unsigned type,
> int enabled)
> {
> @@ -6011,7 +6018,7 @@ int tonga_dpm_set_interrupt_state(void *private_data,
> return 0;
> }
>
> -int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
> +static int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
> const void *thermal_interrupt_info)
> {
> int result;
> @@ -6038,7 +6045,8 @@ int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
> return 0;
> }
>
> -bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
> +static bool tonga_check_smc_update_required_for_display_configuration(
> + struct pp_hwmgr *hwmgr)
> {
> struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
> bool is_update_required = false;
> @@ -6066,7 +6074,9 @@ static inline bool tonga_are_power_levels_equal(const struct tonga_performance_l
> (pl1->pcie_lane == pl2->pcie_lane));
> }
>
> -int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
> +static int tonga_check_states_equal(struct pp_hwmgr *hwmgr,
> + const struct pp_hw_power_state *pstate1,
> + const struct pp_hw_power_state *pstate2, bool *equal)
> {
> const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1);
> const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
> index 47ef1ca..0cd42ae 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
> @@ -138,7 +138,7 @@ int tonga_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -int tonga_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
> +static int tonga_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
> {
> int result;
>
> @@ -360,7 +360,8 @@ int tonga_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
> * @param Result the last failure code
> * @return result from set temperature range routine
> */
> -int tf_tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result)
> +static int tf_tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
> + void *input, void *output, void *storage, int result)
> {
> struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
> SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
> @@ -451,7 +452,9 @@ int tf_tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, void *
> * @param Result the last failure code
> * @return result from set temperature range routine
> */
> -int tf_tonga_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result)
> +static int
> +tf_tonga_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, void *input,
> + void *output, void *storage, int result)
> {
> /* If the fantable setup has failed we could have disabled PHM_PlatformCaps_MicrocodeFanControl even after this function was included in the table.
> * Make sure that we still think controlling the fan is OK.
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> index 8e52a2e..96fc38e 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> @@ -187,7 +187,7 @@ int fiji_copy_bytes_to_smc(struct pp_smumgr *smumgr,
> return 0;
> }
>
> -int fiji_program_jump_on_start(struct pp_smumgr *smumgr)
> +static int fiji_program_jump_on_start(struct pp_smumgr *smumgr)
> {
> static const unsigned char data[] = { 0xE0, 0x00, 0x80, 0x40 };
>
> @@ -201,7 +201,7 @@ int fiji_program_jump_on_start(struct pp_smumgr *smumgr)
> *
> * @param smumgr the address of the powerplay hardware manager.
> */
> -bool fiji_is_smc_ram_running(struct pp_smumgr *smumgr)
> +static bool fiji_is_smc_ram_running(struct pp_smumgr *smumgr)
> {
> return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
> CGS_IND_REG__SMC,
> @@ -217,7 +217,7 @@ bool fiji_is_smc_ram_running(struct pp_smumgr *smumgr)
> * @param msg the message to send.
> * @return The response that came from the SMC.
> */
> -int fiji_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
> +static int fiji_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
> {
> if (!fiji_is_smc_ram_running(smumgr))
> return -1;
> @@ -240,7 +240,7 @@ int fiji_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
> * @param parameter: the parameter to send
> * @return The response that came from the SMC.
> */
> -int fiji_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
> +static int fiji_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
> uint16_t msg, uint32_t parameter)
> {
> if (!fiji_is_smc_ram_running(smumgr))
> @@ -267,7 +267,7 @@ int fiji_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
> * @param parameter: the parameter to send
> * @return The response that came from the SMC.
> */
> -int fiji_send_msg_to_smc_with_parameter_without_waiting(
> +static int fiji_send_msg_to_smc_with_parameter_without_waiting(
> struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
> {
> if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) {
> @@ -661,7 +661,7 @@ static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
> return result;
> }
>
> -int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
> +static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
> {
> int i, result = -1;
> uint32_t reg, data;
> @@ -726,7 +726,7 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
> return result;
> }
>
> -int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
> +static int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
> {
> int result = 0;
> uint32_t table_start;
> @@ -762,7 +762,7 @@ int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
> return result;
> }
>
> -int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
> +static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
> {
> int32_t vr_config;
> uint32_t table_start;
> @@ -801,7 +801,7 @@ int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
> }
>
> /* Work in Progress */
> -int fiji_restore_vft_table(struct pp_smumgr *smumgr)
> +static int fiji_restore_vft_table(struct pp_smumgr *smumgr)
> {
> struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
>
> @@ -813,7 +813,7 @@ int fiji_restore_vft_table(struct pp_smumgr *smumgr)
> }
>
> /* Work in Progress */
> -int fiji_save_vft_table(struct pp_smumgr *smumgr)
> +static int fiji_save_vft_table(struct pp_smumgr *smumgr)
> {
> struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
>
> @@ -824,7 +824,7 @@ int fiji_save_vft_table(struct pp_smumgr *smumgr)
> return -EINVAL;
> }
>
> -int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
> +static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
> {
> struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> index f506583..e5a2b0c 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> @@ -164,7 +164,7 @@ static void iceland_pp_reset_smc(struct pp_smumgr *smumgr)
> rst_reg, 1);
> }
>
> -int iceland_program_jump_on_start(struct pp_smumgr *smumgr)
> +static int iceland_program_jump_on_start(struct pp_smumgr *smumgr)
> {
> static const unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> index 8047ad2..2cd0d78 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> @@ -211,7 +211,7 @@ static int polaris10_program_jump_on_start(struct pp_smumgr *smumgr)
> *
> * @param smumgr the address of the powerplay hardware manager.
> */
> -bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr)
> +static bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr)
> {
> return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
> && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
> @@ -236,7 +236,8 @@ static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
> * @param msg the message to send.
> * @return The response that came from the SMC.
> */
> -int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
> +static int
> +polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
> {
> int ret;
>
> @@ -271,7 +272,9 @@ int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
> * @param msg the message to send.
> * @return Always return 0.
> */
> -int polaris10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
> +static int
> +polaris10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr,
> + uint16_t msg)
> {
> cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
>
> @@ -286,7 +289,9 @@ int polaris10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t
> * @param parameter: the parameter to send
> * @return The response that came from the SMC.
> */
> -int polaris10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
> +static int
> +polaris10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
> + uint16_t msg, uint32_t parameter)
> {
> if (!polaris10_is_smc_ram_running(smumgr)) {
> return -1;
> @@ -315,7 +320,7 @@ int polaris10_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *s
> return polaris10_send_msg_to_smc_without_waiting(smumgr, msg);
> }
>
> -int polaris10_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
> +static int polaris10_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
> {
> cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
>
> @@ -479,7 +484,7 @@ int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
> }
>
>
> -int polaris10_smu_fini(struct pp_smumgr *smumgr)
> +static int polaris10_smu_fini(struct pp_smumgr *smumgr)
> {
> if (smumgr->backend) {
> kfree(smumgr->backend);
> @@ -685,7 +690,7 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr)
> }
>
>
> -int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
> +static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
> {
> uint32_t vr_config;
> uint32_t dpm_table_start;
> @@ -739,7 +744,8 @@ int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
> return 0;
> }
>
> -int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
> +static int
> +polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
> {
> struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> index f42c536..2efdd98 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> @@ -143,7 +143,7 @@ int tonga_copy_bytes_to_smc(struct pp_smumgr *smumgr,
> }
>
>
> -int tonga_program_jump_on_start(struct pp_smumgr *smumgr)
> +static int tonga_program_jump_on_start(struct pp_smumgr *smumgr)
> {
> static const unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
>
>
Attachment:
signature.asc
Description: OpenPGP digital signature
_______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
