On 2016-09-05 01:46, Meng Yi wrote:
>> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
>>
>> Since using clk_register_divider to setup the pixel clock, regmap is no longer
>> used. Regmap did take care of DCU using different endianness. Check
>> endianness using the device-tree property "big-endian" to determine the
>> location of DIV_RATIO.
>>
>> Cc: stable@xxxxxxxxxxxxxxx
>> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
>> clock divider")
>> Reported-by: Meng Yi <meng.yi@xxxxxxx>
>> Signed-off-by: Stefan Agner <stefan@xxxxxxxx>
<snip>
>
> Tested-by: Meng Yi <meng.yi@xxxxxxx>
> On LS1021A-TWR board.
Thanks, applied!
--
Stefan
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