Am Freitag, den 26.08.2016, 15:30 +0800 schrieb Liu Ying: > According to basic tests, it looks there is no issue if we don't wait for > DMFC FIFO to clear when disabling DMFC channel. NXP BSP doesn't do that, > either. This patch is needed to avoid the annoying warning caused by a > timeout on waiting for the FIFO to clear after we add the new > DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET flag to the imx-drm driver > which changes the procedure to disable display channel slightly. I suppose the reason this happens is that now DC/DI are disabled first, so the DC can't drain the FIFO anymore. If the FIFO is properly reset when reenabling the DMFC, this shouldn't have any ill effects. regards Philipp _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
