Some panels only accept bpc (bit per color) 6-bit.
But, the default bpc in mt8173 display data path is 8-bit.
If we didn't enable dithering function to convert bpc,
display cannot show the smooth grayscale image.
In mt8173, the dithering function in OD (OverDrive) and
GAMMA module, we have to config them with
connector->display_mode.bpc when CRTC initial.
1. Clear the default value at *_DITHER_5 and *_DITHER_7 register.
2. Calculate the LSB_ERR_SHIFT bits and ADD_LSHIFT bits two values.
i.e. Input bpc of OD is 10 bits, we assume the bpc of panel is 6-bit,
so, we need to set 4-bit to LSB_ERR_SHIFT and ADD_LSHIFT bits respectively.
3. Then, set the OD or GAMMA to dithering mode depends on path-1 or path-2.
Signed-off-by: Bibby Hsieh <bibby.hsieh@xxxxxxxxxxxx>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 +++++++++++++++++++++++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 6 ++--
5 files changed, 64 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 8f62671f..019b7ca 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -103,7 +103,8 @@ static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
}
static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
- unsigned int h, unsigned int vrefresh)
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc)
{
if (w != 0 && h != 0)
writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 5fb80cb..0df05f9 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -106,7 +106,8 @@ static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
}
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
- unsigned int height, unsigned int vrefresh)
+ unsigned int height, unsigned int vrefresh,
+ unsigned int bpc)
{
unsigned int threshold;
unsigned int reg;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 1b38406..96c1b31 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -52,6 +52,7 @@ struct mtk_drm_crtc {
struct mtk_disp_mutex *mutex;
unsigned int ddp_comp_nr;
struct mtk_ddp_comp **ddp_comp;
+ unsigned int bpc;
};
struct mtk_crtc_state {
@@ -232,6 +233,8 @@ static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
{
struct drm_crtc *crtc = &mtk_crtc->base;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
unsigned int width, height, vrefresh;
int ret;
int i;
@@ -243,6 +246,15 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
width = crtc->state->adjusted_mode.hdisplay;
height = crtc->state->adjusted_mode.vdisplay;
vrefresh = crtc->state->adjusted_mode.vrefresh;
+ drm_for_each_encoder(encoder, crtc->dev) {
+ if (encoder->crtc != crtc)
+ continue;
+ drm_for_each_connector(connector, crtc->dev) {
+ if (connector->encoder != encoder)
+ continue;
+ mtk_crtc->bpc = connector->display_info.bpc;
+ }
+ }
ret = pm_runtime_get_sync(crtc->dev->dev);
if (ret < 0) {
@@ -276,7 +288,8 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
- mtk_ddp_comp_config(comp, width, height, vrefresh);
+ mtk_ddp_comp_config(comp, width, height, vrefresh,
+ mtk_crtc->bpc);
mtk_ddp_comp_start(comp);
}
@@ -475,7 +488,8 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
if (state->pending_config) {
mtk_ddp_comp_config(ovl, state->pending_width,
state->pending_height,
- state->pending_vrefresh);
+ state->pending_vrefresh,
+ mtk_crtc->bpc);
state->pending_config = false;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 3fd5141..c574f6d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -31,6 +31,10 @@
#define DISP_OD_INTSTA 0x000c
#define DISP_OD_CFG 0x0020
#define DISP_OD_SIZE 0x0030
+#define DISP_OD_DITHER_5 0x0114
+#define DISP_OD_DITHER_7 0x011c
+#define DISP_OD_DITHER_15 0x013c
+#define DISP_OD_DITHER_16 0x0140
#define DISP_REG_UFO_START 0x0000
@@ -52,14 +56,31 @@
#define GAMMA_LUT_EN BIT(1)
#define OD_RELAY_MODE BIT(0)
+#define OD_DITHERING BIT(2)
#define UFO_BYPASS BIT(2)
#define COLOR_BYPASS_ALL BIT(7)
#define COLOR_SEQ_SEL BIT(13)
+#define DITHERING_ALGORITHM_EN BIT(0)
+
+#define DITHERING_LSB_ERR_SHIFT_R(bits) ((bits) << 28)
+#define DITHERING_OVFLW_R(bits) ((bits) << 24)
+#define DITHERING_ADD_LSHIFT_R(bits) ((bits) << 20)
+#define DITHERING_INPUT_RSHIFT_R(bits) ((bits) << 16)
+#define DITHERING_LSB_ERR_SHIFT_B(bits) ((bits) << 28)
+#define DITHERING_OVFLW_B(bits) ((bits) << 24)
+#define DITHERING_ADD_LSHIFT_B(bits) ((bits) << 20)
+#define DITHERING_INPUT_RSHIFT_B(bits) ((bits) << 16)
+#define DITHERING_LSB_ERR_SHIFT_G(bits) ((bits) << 12)
+#define DITHERING_OVFLW_G(bits) ((bits) << 8)
+#define DITHERING_ADD_LSHIFT_G(bits) ((bits) << 4)
+#define DITHERING_INPUT_RSHIFT_G(bits) (bits)
+
static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
- unsigned int h, unsigned int vrefresh)
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc)
{
writel(w, comp->regs + DISP_COLOR_WIDTH);
writel(h, comp->regs + DISP_COLOR_HEIGHT);
@@ -73,9 +94,25 @@ static void mtk_color_start(struct mtk_ddp_comp *comp)
}
static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
- unsigned int h, unsigned int vrefresh)
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc)
{
writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
+ if (bpc < 10) {
+ writel(0, comp->regs + DISP_OD_DITHER_5);
+ writel(0, comp->regs + DISP_OD_DITHER_7);
+ writel(DITHERING_LSB_ERR_SHIFT_R(10 - bpc) |
+ DITHERING_ADD_LSHIFT_R(10 - bpc) |
+ DITHERING_ALGORITHM_EN, comp->regs + DISP_OD_DITHER_15);
+ writel(DITHERING_LSB_ERR_SHIFT_B(10 - bpc) |
+ DITHERING_ADD_LSHIFT_B(10 - bpc) |
+ DITHERING_LSB_ERR_SHIFT_G(10 - bpc) |
+ DITHERING_ADD_LSHIFT_G(10 - bpc),
+ comp->regs + DISP_OD_DITHER_16);
+ writel(OD_DITHERING, comp->regs + DISP_OD_CFG);
+ } else {
+ writel(OD_RELAY_MODE, comp->regs + DISP_OD_CFG);
+ }
}
static void mtk_od_start(struct mtk_ddp_comp *comp)
@@ -90,7 +127,8 @@ static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
}
static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
- unsigned int h, unsigned int vrefresh)
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc)
{
writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 0832179..02ca1be 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -64,7 +64,7 @@ struct mtk_ddp_comp;
struct mtk_ddp_comp_funcs {
void (*config)(struct mtk_ddp_comp *comp, unsigned int w,
- unsigned int h, unsigned int vrefresh);
+ unsigned int h, unsigned int vrefresh, unsigned int bpc);
void (*start)(struct mtk_ddp_comp *comp);
void (*stop)(struct mtk_ddp_comp *comp);
void (*enable_vblank)(struct mtk_ddp_comp *comp, struct drm_crtc *crtc);
@@ -88,10 +88,10 @@ struct mtk_ddp_comp {
static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp,
unsigned int w, unsigned int h,
- unsigned int vrefresh)
+ unsigned int vrefresh, unsigned int bpc)
{
if (comp->funcs && comp->funcs->config)
- comp->funcs->config(comp, w, h, vrefresh);
+ comp->funcs->config(comp, w, h, vrefresh, bpc);
}
static inline void mtk_ddp_comp_start(struct mtk_ddp_comp *comp)
--
1.7.9.5
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