Instead of conditioning planes update based on the hardware device
state, use the CRTC state stored in the atomic state. This reduces the
dependency from the DRM layer to the DSS layer.
Signed-off-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/omapdrm/omap_crtc.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c
index 6359d7933b93..4c56d6a68390 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.c
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
@@ -381,18 +381,23 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
WARN_ON(omap_crtc->vblank_irq.registered);
- if (dispc_mgr_is_enabled(omap_crtc->channel)) {
+ /*
+ * Only flush the CRTC if it is currently active. CRTCs that require a
+ * mode set are disabled prior plane updates and enabled afterwards.
+ * They are thus not active, regardless of what their state report.
+ */
+ if (!crtc->state->active || drm_atomic_crtc_needs_modeset(crtc->state))
+ return;
- DBG("%s: GO", omap_crtc->name);
+ DBG("%s: GO", omap_crtc->name);
- rmb();
- WARN_ON(omap_crtc->pending);
- omap_crtc->pending = true;
- wmb();
+ rmb();
+ WARN_ON(omap_crtc->pending);
+ omap_crtc->pending = true;
+ wmb();
- dispc_mgr_go(omap_crtc->channel);
- omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
- }
+ dispc_mgr_go(omap_crtc->channel);
+ omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
}
static bool omap_crtc_is_plane_prop(struct drm_device *dev,
--
Regards,
Laurent Pinchart
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