On 2016-05-26 02:11, Alexander Stein wrote:
> On Thursday 26 May 2016 08:23:42, Meng Yi wrote:
>> Hi Mark,
>>
>> > You've not specifically described the problem here - what are the
>> > endiannesses of both the CPU and the device you're talking to? What
>> > specifically is the endianess problem you are seeing, what are you seeing
>> > and what do you expect to see?
>>
>> The CPU is little endian and the device DCU is big endian, specified
>> big-endian in DTS,
>>
>> And here is my DTS and regmap_config,
>>
>> Specified "big-endian" in DTS,
>>
>> dcu: dcu@2ce0000 {
>> compatible = "fsl,ls1021a-dcu";
>> reg = <0x0 0x2ce0000 0x0 0x10000>;
>> interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
>> clocks = <&platform_clk 0>;
>> clock-names = "dcu";
>> big-endian;
>> status = "disabled";
>> };
>>
>> I can't tell the difference of "reg_format_endian" and " val_format_endian
>> ", so I had tried four conditions. And all failed.
>>
>> static const struct regmap_config fsl_dcu_regmap_config = {
>> .reg_bits = 32,
>> .reg_stride = 4,
>> .val_bits = 32,
>> .cache_type = REGCACHE_RBTREE,
>
> This needs to be a flat cache. See
> https://lists.freedesktop.org/archives/dri-devel/2016-January/099121.html
> or https://lkml.org/lkml/2016/3/24/281
> max_register also needs an appropriate value.
Ok, since the complete set which switches to the atomic helper is not
stable material (and also won't make it into 4.7 anymore), I created a
seperate bugfix now:
https://lists.freedesktop.org/archives/dri-devel/2016-June/109625.html
What I don't quite get yet is the REGCACHE_FLAT influencing the
endianness behavior?
If it is, Meng, can you test again with v4.7-rc1 + the FLAT cache patch
above?
--
Stefan
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