On Tue, May 3, 2011 at 8:17 PM, Dave Airlie <airlied@xxxxxxxxx> wrote:
> From: Alex Deucher <alexdeucher@xxxxxxxxx>
>
> Out of the entire GART/VM subsystem, the hw designers changed
> the location of 3 regs.
>
> v2: airlied: add parameter for userspace to work from.
>
> Signed-off-by: Alex Deucher <alexdeucher@xxxxxxxxx>
> Signed-off-by: Jerome Glisse <jglisse@xxxxxxxxxx>
> Cc: stable@xxxxxxxxxx
> Signed-off-by: Dave Airlie <airlied@xxxxxxxxxx>
Looks good.
Signed-off-by: Alex Deucher <alexdeucher@xxxxxxxxx>
> ---
> drivers/gpu/drm/radeon/evergreen.c | 17 +++++++++--------
> drivers/gpu/drm/radeon/evergreend.h | 5 +++++
> drivers/gpu/drm/radeon/radeon_kms.c | 3 +++
> include/drm/radeon_drm.h | 1 +
> 4 files changed, 18 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
> index e9bc135..c20eac3 100644
> --- a/drivers/gpu/drm/radeon/evergreen.c
> +++ b/drivers/gpu/drm/radeon/evergreen.c
> @@ -862,9 +862,15 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
> SYSTEM_ACCESS_MODE_NOT_IN_SYS |
> SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
> EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
> - WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
> - WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
> - WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
> + if (rdev->flags & RADEON_IS_IGP) {
> + WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
> + WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
> + WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
> + } else {
> + WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
> + WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
> + WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
> + }
> WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
> WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
> WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
> @@ -2923,11 +2929,6 @@ static int evergreen_startup(struct radeon_device *rdev)
> rdev->asic->copy = NULL;
> dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
> }
> - /* XXX: ontario has problems blitting to gart at the moment */
> - if (rdev->family == CHIP_PALM) {
> - rdev->asic->copy = NULL;
> - radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
> - }
>
> /* allocate wb buffer */
> r = radeon_wb_init(rdev);
> diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
> index 9aaa3f0..9453384 100644
> --- a/drivers/gpu/drm/radeon/evergreend.h
> +++ b/drivers/gpu/drm/radeon/evergreend.h
> @@ -221,6 +221,11 @@
> #define MC_VM_MD_L1_TLB0_CNTL 0x2654
> #define MC_VM_MD_L1_TLB1_CNTL 0x2658
> #define MC_VM_MD_L1_TLB2_CNTL 0x265C
> +
> +#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C
> +#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
> +#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664
> +
> #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
> #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
> #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
> diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
> index 871df03..bd58af6 100644
> --- a/drivers/gpu/drm/radeon/radeon_kms.c
> +++ b/drivers/gpu/drm/radeon/radeon_kms.c
> @@ -234,6 +234,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
> return -EINVAL;
> }
> break;
> + case RADEON_INFO_FUSION_GART_WORKING:
> + value = 1;
> + break;
> default:
> DRM_DEBUG_KMS("Invalid request %d\n", info->request);
> return -EINVAL;
> diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
> index 7aa5ddd..787f7b6 100644
> --- a/include/drm/radeon_drm.h
> +++ b/include/drm/radeon_drm.h
> @@ -910,6 +910,7 @@ struct drm_radeon_cs {
> #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */
> #define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */
> #define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */
> +#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */
>
> struct drm_radeon_info {
> uint32_t request;
> --
> 1.7.1
>
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>
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