[Bug 95206] Display port bandwidth regression

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Comment # 8 on bug 95206 from
Hi,

I've bisected the problem down to the following commit to the mainline kernel
(see below). Can I help with some further information?

092c96a8ab9d1bd60ada2ed385cc364ce084180e is the first bad commit
commit 092c96a8ab9d1bd60ada2ed385cc364ce084180e
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Thu Dec 17 10:23:34 2015 -0500

    drm/radeon: fix dp link rate selection (v2)

    Need to properly handle the max link rate in the dpcd.
    This prevents some cases where 5.4 Ghz is selected when
    it shouldn't be.

    v2: simplify logic, add array bounds check

    Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

:040000 040000 c27fa6e02534c3ef9f53c3c954fa936b1e414cb3
0be8f64ebe28383efa39ebce68247b148f4a78f2 M    drivers


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