On Fri, Apr 15, 2016 at 03:34:41PM -0700, Stephen Boyd wrote: > On 03/23, Maxime Ripard wrote: > > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and > > PLL7, clocked from a 3MHz oscillator, that drives the display related > > clocks (GPU, display engine, TCON, etc.) > > > > Add a driver for it. > > > > Acked-by: Rob Herring <robh@xxxxxxxxxx> > > Acked-by: Chen-Yu Tsai <wens@xxxxxxxx> > > Signed-off-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> > > --- > > Acked-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx> Applied, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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