-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 02/26/2016 03:29 PM, Timothy Pearson wrote: > During DRAM initialization on certain ASpeed devices, an incorrect > bit (bit 10) was checked in the "SDRAM Bus Width Status" register > to determine DRAM width. > > Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. > > Signed-off-by: Timothy Pearson <tpearson@xxxxxxxxxxxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/ast/ast_main.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c > index 9759009..b1480ac 100644 > --- a/drivers/gpu/drm/ast/ast_main.c > +++ b/drivers/gpu/drm/ast/ast_main.c > @@ -227,7 +227,7 @@ static int ast_get_dram_info(struct drm_device *dev) > } while (ast_read32(ast, 0x10000) != 0x01); > data = ast_read32(ast, 0x10004); > > - if (data & 0x400) > + if (data & 0x40) > ast->dram_bus_width = 16; > else > ast->dram_bus_width = 32; Just wanted to give this a bump since I have not received any feedback on it. Thanks! - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) http://www.raptorengineeringinc.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJW1eZsAAoJEK+E3vEXDOFbusEH/2HXEJ4MfTsV5FRmXQpqv4rh iqGbd/whbOl9HAwWwz1DgfDIoqjBvBUlrq4C/UEmkFIVo5cqZQQsUIHejsz/GEIx 2mpf1pTIaNnW8oK6w8QX2wxFiV4XOUallOHh+OPmUTZQFpDiJH7MgqWhZ7HNEsRi lyjYILfPw5Q1cRHKxCn+IPGgStPDr6ds5EbAlNNZKTgdRuUoPLW3LLAyZ6Gtjkwr FVSe4uIiLC1/HNlrhryFvsAPA6N5hUqFDxAZ7pLFKoRLJpteJnhr5tBJLnwScZlN 6zYZRmDieHHIomFK462SGo8lhyxc8bnbJkYuEKvNvOzdI7B4rriCUMWpIgw1ISg= =JWPN -----END PGP SIGNATURE----- _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
