Quoting Philipp Zabel (2016-02-17 03:28:50)
> This mux is supposed to select a fitting divider after the PLL
> is already set to the correct rate.
>
> Signed-off-by: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
> Acked-by: James Liao <jamesjj.liao@xxxxxxxxxxxx>
Looks good to me.
Regards,
Mike
> ---
> Changes since v10:
> - Add comments about MUX_GATE rate change propagation
> ---
> drivers/clk/mediatek/clk-mt8173.c | 6 +++++-
> drivers/clk/mediatek/clk-mtk.h | 15 +++++++++++++--
> 2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
> index 227e356..85c0bfc 100644
> --- a/drivers/clk/mediatek/clk-mt8173.c
> +++ b/drivers/clk/mediatek/clk-mt8173.c
> @@ -558,7 +558,11 @@ static const struct mtk_composite top_muxes[] __initconst = {
> MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
> MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),
> /* CLK_CFG_6 */
> - MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7),
> + /*
> + * The dpi0_sel clock should not propagate rate changes to its parent
> + * clock so the dpi driver can have full control over PLL and divider.
> + */
> + MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7, 0),
> MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
> MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
> MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 32d2e45..9f24fcf 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -83,7 +83,11 @@ struct mtk_composite {
> signed char num_parents;
> };
>
> -#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \
> +/*
> + * In case the rate change propagation to parent clocks is undesirable,
> + * this macro allows to specify the clock flags manually.
> + */
> +#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) { \
> .id = _id, \
> .name = _name, \
> .mux_reg = _reg, \
> @@ -94,9 +98,16 @@ struct mtk_composite {
> .divider_shift = -1, \
> .parent_names = _parents, \
> .num_parents = ARRAY_SIZE(_parents), \
> - .flags = CLK_SET_RATE_PARENT, \
> + .flags = _flags, \
> }
>
> +/*
> + * Unless necessary, all MUX_GATE clocks propagate rate changes to their
> + * parent clock by default.
> + */
> +#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \
> + MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, CLK_SET_RATE_PARENT)
> +
> #define MUX(_id, _name, _parents, _reg, _shift, _width) { \
> .id = _id, \
> .name = _name, \
> --
> 2.7.0
>
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