On 22 February 2011 18:25, Daniel Vetter <daniel.vetter@xxxxxxxx> wrote:
> It looks like gen2 has a peculiar interleaved 2-row inter-tile
> layout. Probably inherited from i81x which had 2kb tiles (which
> naturally fit an even-number-of-tile-rows scheme to fit onto 4kb
> pages). There is no other mention of this in any docs (also not
> in the Intel internal documention according to Chris Wilson).
Giving that lack of documentation, could you put some more comments in the code?
so that nobody cleans out that "strange workaround" in 6 monthes...
> @@ -215,6 +215,20 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> Â Â Â Â Â Â Â Â}
> Â Â Â Â}
>
> + Â Â Â if (IS_GEN2(dev) ||
> + Â Â Â Â Â (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
> + Â Â Â Â Â Â Â tile_height = 32;
> + Â Â Â else
> + Â Â Â Â Â Â Â tile_height = 8;
> + Â Â Â /* i8xx is strange: It has 2 interleaved rows of tiles, so needs an even
> + Â Â Â Â* number of tile rows. */
> + Â Â Â if (IS_GEN2(dev))
> + Â Â Â Â Â Â Â tile_height *= 2;
> +
> + Â Â Â /* Size needs to be aligned to a full tile row */
> + Â Â Â if (size & (tile_height * stride - 1))
> + Â Â Â Â Â Â Â return false;
> +
> Â Â Â Â/* 965+ just needs multiples of tile width */
> Â Â Â Âif (INTEL_INFO(dev)->gen >= 4) {
> Â Â Â Â Â Â Â Âif (stride & (tile_width - 1))
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