On Tue, 14 Dec 2010 12:09:49 -0800, "Segovia, Benjamin" <benjamin.segovia@xxxxxxxxx> wrote: > Perfect. It is still a good temporary solution. For coherency, my goal is top ensure it without the need of MI_FLUSH or pipe control. So, EUs must be able to do it themselves > For ILK > * on CPU, I used _mm_clflush (as the kernel does btw) to go through memory > * on EUs, I used the render cache flush command Fo ILK: Note that for writes, if you're poking into memory (drm_intel_bo_map), then clflush is not sufficient, you also need to flush the GWB. Check out the agp chipset flush code. If you're going through GTT (drm_intel_gem_bo_map_gtt), then you don't need clfush, just a posting read. If you're trying to get streaming write performance, the best way is probably the GTT. If you're trying to get streaming read performance, the best way is likely also the GTT with movntdqa.
Attachment:
pgp3GQqNg45wk.pgp
Description: PGP signature
_______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
