On Tue, 24 Aug 2010 16:56:16 +0100
Sitsofe Wheeler <sitsofe@xxxxxxxxx> wrote:
> With the extra intel_wait_for_vblank added in commit
> 9d0498a2bf7455159b317f19531a3e5db2ecc9c4 periodic stalls were being
> triggered (which were detected by i915_hangcheck_elapsed). Partially
> revert this change for now.
>
> Signed-off-by: Sitsofe Wheeler <sitsofe@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 ++++--
> 1 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 116d938..534f1fa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2379,8 +2379,10 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
> I915_READ(dspbase_reg);
> }
>
> - /* Wait for vblank for the disable to take effect */
> - intel_wait_for_vblank_off(dev, pipe);
> + if (!IS_I9XX(dev)) {
> + /* Wait for vblank for the disable to take effect */
> + intel_wait_for_vblank_off(dev, pipe);
> + }
>
> /* Don't disable pipe A or pipe A PLLs if needed */
> if (pipeconf_reg == PIPEACONF &&
Hm why would we be triggering the hangcheck timer due to this code?
I'd rather figure that out and fix it before covering it up like this.
Wait for vblank off will spin until the display line reg stops
incrementing, so it's important that we flush any previous writes to
shut off the pipe before waiting. So adding a POSTING_READ() above it
might help? But that still doesn't explain why it would cause the
hangcheck timer to notice a hang...
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
dri-devel mailing list
dri-devel@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/dri-devel
