Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX75 platform. Since there is no "aon" clock in SDX75, a dummy clock is provided. Signed-off-by: Kaushal Kumar <quic_kaushalk@xxxxxxxxxxx> --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index e3a0ee661c4a..9c43b14a0594 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -37,6 +37,12 @@ clock-frequency = <32764>; #clock-cells = <0>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; }; cpus { @@ -894,6 +900,24 @@ status = "disabled"; }; + qpic_nand: nand-controller@1cc8000 { + compatible = "qcom,sdx75-nand", "qcom,sdx55-nand"; + reg = <0x0 0x01cc8000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + iommus = <&apps_smmu 0x100 0x3>; + dma-coherent; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; -- 2.17.1