Look good! Thanks > -----Original Message----- > From: Larisa Ileana Grigore (OSS) <larisa.grigore@xxxxxxxxxxx> > Sent: Monday, December 16, 2024 1:58 AM > To: Frank Li <frank.li@xxxxxxx> > Cc: dmaengine@xxxxxxxxxxxxxxx; imx@xxxxxxxxxxxxxxx; linux- > kernel@xxxxxxxxxxxxxxx; dl-S32 <S32@xxxxxxx>; Christophe Lizzi > <clizzi@xxxxxxxxxx>; Alberto Ruiz <aruizrui@xxxxxxxxxx>; Enric Balletbo > <eballetb@xxxxxxxxxx>; Larisa Ileana Grigore (OSS) > <larisa.grigore@xxxxxxxxxxx> > Subject: [PATCH 0/8] Add eDMAv3 support for S32G2/S32G3 SoCs > > S32G2 and S32G3 SoCs share the eDMAv3 module with i.MX SoCs, with some > hardware > integration particularities. > > S32G2/S32G3 includes two system eDMA instances based on v3 version, each > of > them integrated with 2 DMAMUX blocks. > Another particularity of these SoCs is that the interrupts are shared > between > channels as follows: > - DMA Channels 0-15 share the 'tx-0-15' interrupt > - DMA Channels 16-31 share the 'tx-16-31' interrupt > - all channels share the 'err' interrupt > > Larisa Grigore (8): > dmaengine: fsl-edma: select of_dma_xlate based on the dmamuxs presence > dmaengine: fsl-edma: remove FSL_EDMA_DRV_SPLIT_REG check when parsing > muxbase > dmaengine: fsl-edma: move eDMAv2 related registers to a new structure > ’edma2_regs’ > dmaengine: fsl-edma: add eDMAv3 registers to edma_regs > dt-bindings: dma: fsl-edma: add nxp,s32g2-edma compatible string > dmaengine: fsl-edma: add support for S32G based platforms > dmaengine: fsl-edma: wait until no hardware request is in progress > dmaengine: fsl-edma: read/write multiple registers in cyclic > transactions > > .../devicetree/bindings/dma/fsl,edma.yaml | 34 +++++ > drivers/dma/fsl-edma-common.c | 112 +++++++++----- > drivers/dma/fsl-edma-common.h | 26 +++- > drivers/dma/fsl-edma-main.c | 137 ++++++++++++++++-- > 4 files changed, 257 insertions(+), 52 deletions(-) > > -- > 2.47.0
