Hi, Manivannan Sadhasivam: Thank you for your reply! On Fri, Jul 05, 2024 at 19:42:41 +0530, Manivannan Sadhasivam wrote: > On Fri, Jul 05, 2024 at 06:57:34PM +0800, zheng.dongxiong wrote: > > Two or more chunks are used in a transfer, > > Consumer cycle only needs to be set on the first transfer. > > > > Can you please reference the section of the spec that mentions this behavior? > > - Mani > Reference: Chapter 6.4.9.1 LL Operation Overview: "Figure 6-23 Linked List Flow for Producer and Consumer" in DesignWare Cores PCI Express Controller Databook (Version 6.00a June 2022) The CCS must be set when L1 is executed for the first time, After an interruption is triggered, CCS does not need to be configured again when L3 is executed. > > Signed-off-by: zheng.dongxiong <zheng.dongxiong@xxxxxxxxxxx> > > --- > > drivers/dma/dw-edma/dw-hdma-v0-core.c | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c > > index 10e8f0715..d77051d1e 100644 > > --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c > > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c > > @@ -262,10 +262,10 @@ static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) > > lower_32_bits(chunk->ll_region.paddr)); > > SET_CH_32(dw, chan->dir, chan->id, llp.msb, > > upper_32_bits(chunk->ll_region.paddr)); > > + /* Set consumer cycle */ > > + SET_CH_32(dw, chan->dir, chan->id, cycle_sync, > > + HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); > > } > > - /* Set consumer cycle */ > > - SET_CH_32(dw, chan->dir, chan->id, cycle_sync, > > - HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); > > > > dw_hdma_v0_sync_ll_data(chunk); > > > > -- > > 2.34.1 > > > Test brief: hdma set chan->ll_max == 1, then user alloc two or more scatterlist, start transfer. -- Regards, dongxiong zheng
