Hello Andy,
On Fri, 2023-07-21 at 17:13 +0300, Andy Shevchenko wrote:
> > + spin_lock_irqsave(&ep93xx_swlock, flags);
> > +
> > + regmap_read(map, EP93XX_SYSCON_DEVCFG, &val);
> > + val &= ~clear_bits;
> > + val |= set_bits;
> > + regmap_write(map, EP93XX_SYSCON_SWLOCK, EP93XX_SWLOCK_MAGICK);
> > + regmap_write(map, EP93XX_SYSCON_DEVCFG, val);
>
> Is this sequence a must?
> I.o.w. can you first supply magic and then update devcfg?
>
> > + spin_unlock_irqrestore(&ep93xx_swlock, flags);
>
> ...
>
> > +void ep93xx_swlocked_update_bits(struct regmap *map, unsigned int reg,
> > + unsigned int mask, unsigned int val)
> > +{
>
> Same Q as above.
EP93xx User Manual [1] has most verbose description of SWLock for ADC
block:
"Writing 0xAA to this register will unlock all locked registers until the
next block access. The ARM lock instruction prefix should be used for the
two consequtive write cycles when writing to locked chip registers."
One may conclude that RmW (two accesses to the particular block) sequence
is not appropriate.
[1] https://cdn.embeddedts.com/resource-attachments/ts-7000_ep9301-ug.pdf
--
Alexander Sverdlin.
