From: Kory Maincent <kory.maincent@xxxxxxxxxxx> When writing the linked list elements and pointer the control need to be written at the end. If the control is written and the SAR and DAR not stored we could face a race condition. Fixes: 7e4b8a4fbe2c ("dmaengine: Add Synopsys eDMA IP version 0 support") Signed-off-by: Kory Maincent <kory.maincent@xxxxxxxxxxx> --- drivers/dma/dw-edma/dw-edma-v0-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c index 2e872d6f2c04..a5d921ef54ec 100644 --- a/drivers/dma/dw-edma/dw-edma-v0-core.c +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c @@ -291,10 +291,10 @@ static void dw_edma_v0_write_ll_data(struct dw_edma_chunk *chunk, int i, } else { struct dw_edma_v0_lli __iomem *lli = chunk->ll_region.vaddr.io + ofs; - writel(control, &lli->control); writel(size, &lli->transfer_size); writeq(sar, &lli->sar.reg); writeq(dar, &lli->dar.reg); + writel(control, &lli->control); } } @@ -311,8 +311,8 @@ static void dw_edma_v0_write_ll_link(struct dw_edma_chunk *chunk, } else { struct dw_edma_v0_llp __iomem *llp = chunk->ll_region.vaddr.io + ofs; - writel(control, &llp->control); writeq(pointer, &llp->llp.reg); + writel(control, &llp->control); } } -- 2.25.1