When multiple channels operate simultaneously, the common register shared by all channels could be set to an unexpected value due to race conditions on SMP machines, resulting in a disaster that DMAC cannot work from then on, therefore, a spinlock is added to avoid this situation.
Take a typical scenario as an example, the execution sequence is as follows:
1. cpu 1 is executing the ISR function dw_axi_dma_interrupt() and axi_dma_irq_enable() has not yet exectuted completely, so the global interrupt enable bit INT_EN is still 0;
2. Thread A is running in another cpu and has completed the execution of axi_dma_ioread32() in axi_dma_enable() called by axi_chan_block_xfer_start(), and then the DMA_CFG register value (with the bit INT_EN cleared) is stored in the variable val;
3. cpu 1 completes the execution of axi_dma_irq_enable() and sets bit INT_EN of DMA_CFG register to 1;
4. Thread A completes the execution of axi_dma_enable() and configures the DMAC_CFG register with variable val which is stored in step 2 above.
As a result, the global interrupt enable bit INT_EN in the DMAC_CFG register is eventually cleared and the DMAC will no longer generates interrupts, and the DMAC cannot work anymore unless the power resume process is triggered according to the current dmac driver.
Signed-off-by: Libing Lei <libing.lei@xxxxxxxxxxxxxxx>
---
Changes since v1:
- an example and more description for this patch
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 20 +++++++++++++++++++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index bf85aa097..7aa53293c 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -108,37 +108,49 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
static inline void axi_dma_disable(struct axi_dma_chip *chip)
{
u32 val;
+ unsigned long flags;
+ spin_lock_irqsave(&chip->lock, flags);
val = axi_dma_ioread32(chip, DMAC_CFG);
val &= ~DMAC_EN_MASK;
axi_dma_iowrite32(chip, DMAC_CFG, val);
+ spin_unlock_irqrestore(&chip->lock, flags);
}
static inline void axi_dma_enable(struct axi_dma_chip *chip)
{
u32 val;
+ unsigned long flags;
+ spin_lock_irqsave(&chip->lock, flags);
val = axi_dma_ioread32(chip, DMAC_CFG);
val |= DMAC_EN_MASK;
axi_dma_iowrite32(chip, DMAC_CFG, val);
+ spin_unlock_irqrestore(&chip->lock, flags);
}
static inline void axi_dma_irq_disable(struct axi_dma_chip *chip)
{
u32 val;
+ unsigned long flags;
+ spin_lock_irqsave(&chip->lock, flags);
val = axi_dma_ioread32(chip, DMAC_CFG);
val &= ~INT_EN_MASK;
axi_dma_iowrite32(chip, DMAC_CFG, val);
+ spin_unlock_irqrestore(&chip->lock, flags);
}
static inline void axi_dma_irq_enable(struct axi_dma_chip *chip)
{
u32 val;
+ unsigned long flags;
+ spin_lock_irqsave(&chip->lock, flags);
val = axi_dma_ioread32(chip, DMAC_CFG);
val |= INT_EN_MASK;
axi_dma_iowrite32(chip, DMAC_CFG, val);
+ spin_unlock_irqrestore(&chip->lock, flags);
}
static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq_mask)
@@ -177,7 +189,9 @@ static inline u32 axi_chan_irq_read(struct axi_dma_chan *chan)
static inline void axi_chan_disable(struct axi_dma_chan *chan)
{
u32 val;
+ unsigned long flags;
+ spin_lock_irqsave(&chan->chip->lock, flags);
val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT);
if (chan->chip->dw->hdata->reg_map_8_channels)
@@ -185,12 +199,15 @@ static inline void axi_chan_disable(struct axi_dma_chan *chan)
else
val |= BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
+ spin_unlock_irqrestore(&chan->chip->lock, flags);
}
static inline void axi_chan_enable(struct axi_dma_chan *chan)
{
u32 val;
+ unsigned long flags;
+ spin_lock_irqsave(&chan->chip->lock, flags);
val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
if (chan->chip->dw->hdata->reg_map_8_channels)
val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
@@ -199,6 +216,7 @@ static inline void axi_chan_enable(struct axi_dma_chan *chan)
val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
+ spin_unlock_irqrestore(&chan->chip->lock, flags);
}
static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan)
@@ -1420,6 +1438,8 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
return ret;
+ spin_lock_init(&chip->lock);
+
dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels,
sizeof(*dw->chan), GFP_KERNEL);
if (!dw->chan)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index e9d5eb0fd..4a8db437e 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -70,6 +70,7 @@ struct axi_dma_chip {
struct clk *core_clk;
struct clk *cfgr_clk;
struct dw_axi_dma *dw;
+ spinlock_t lock;
};
/* LLI == Linked List Item */
--
2.17.1
