Add the dma controller node for the Starfive JH7110 SoC.
Signed-off-by: Walker Chen <walker.chen@xxxxxxxxxxxxxxxx>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 697ab59191a1..191b6add72c8 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -510,6 +510,24 @@
#gpio-cells = <2>;
};
+ dma: dma-controller@16050000 {
+ compatible = "starfive,jh7110-axi-dma";
+ reg = <0x0 0x16050000 0x0 0x10000>;
+ clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
+ <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
+ clock-names = "core-clk", "cfgr-clk";
+ resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
+ <&stgcrg JH7110_STGRST_DMA1P_AHB>;
+ interrupts = <73>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <1>;
+ snps,data-width = <3>;
+ snps,block-size = <65536 65536 65536 65536>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <16>;
+ };
+
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
--
2.17.1
